I am using Xilinx ISE 8.1i on Linux.
I have a bunch of Verilog and project files that I need to check in to our version control system (Perforce) so others can work on them as well.
How do file paths in the project files are handled? For example, when I work on the project the files are under /home/myname/... but when somebody else opens the project he sees the files under /home/othername/...
Can I have relative references from the project file to the source files?
Any other suggestion?
Thanks,
Joe