I upgraded my Modelsim XE-III 6.2c starter edition to Modelsm XE-III 6.2g starter edition. Before isntalling the new software, I uninstalled 6.2c (from Control Panel), and then I deleted the \modelsim_xe_starter directory on my hard-drive.
After the upgrade, I recycled the license.dat file from the old modelsim starter edition. (The license checker says it's valid.) I tried running some Systemverilog testbenches I had... all of them produce the same fatal error. I can compile the code without problem. But when I try to start the simulation (using the 'vsim' command from the Modelsim command-line), I get the following error message:
\modelsiim_xe_starter\win32xeoem/../sv_std is not compiled with XE simulator.
My Systemverilog testbenches have a combination of Verilog-2001 and Systemverilog modules, but I tried a simple testcase with just a single Systemverilog module -- same problem. This was just a simple .sv file with an interface declaration (but no 'advanced' features that require the Questa license.) I also compiled a simple (single-file) VHDL testbench and (single-file) Verilog-2001 testbench. Both compiled and simulated just fine.
i was going to suggest buying a few XE-III (full) licenses, but that was contingent upon, apparently, an undocumented/unofficial support for Systemverilog. Now, I'll probably suggest getting (Mentor) Modelsim-PE.
Anyway, Modelsim XE-III 6.2c starter-edition ran Systemverilog simulations just fine. So did Xilinx remove this feature from XE-III 6.2g? Nowhere in Xilinx's online documentation, does Xilinx claim to support Systemverilog. But I'd like to get a definitive/official answer.