ModelSim XE problems with a VHDL coregen in a Virtex 5

I'm getting a fatal error when I try and simulate a Virtex 5 VHDL project with a block memory core built with coregen. The Virtex 5 Coregen is only allowing Block Memory Generator V2.6 to be used. I see these files in the $XILINX\vhdl\src\XilinxCoreLib directory, but they do not show up in the ModelSim workspace under xilinxcorelib which only goes up to blk_mem_gen_v2_4. Does anyone know what I need to do to get ModelSim to start using these (newer) block mem gen files?

Thanks

Dan