Xilinx ISE 8.2i service pack 3 ModelSim XE III 6.1e VHDL system
When I build a block ram using CoreGen in Xilinx ISE it produces the VHDL file and the Verilog file. When ModelSim sees the verilog file it grabs it and trys to use it but then errors out saying this version of ModelSim does not support a mixed design of both VHDL and Verilog. If I go in and delete the Verilog files everything works fine. This did not happen until I recently updated my software (both Xilinx ISE and ModelSim).
Anyone else run into this problem and maybe have a fix for it?
Hi Dan, Modelsim itself is blind and neither sees files nor grabs them without being told to do so. :-) You are probably starting Modelsim from the ISE Project Navigator. PN creates a script for Modelsim (*.fdo). This script tells Modelsim which files to compile and what else shall be done. The real problem is that good old bilangual ISE favors verilog when converting or searching for files. Try to create a schematic and simulate it. Guess what, it will be converted to a verilog *.vf file. Really great, when you are doing VHDL-Designs and your unilingual Modelsim XE is installed with VHDL.
This behavior of ISE PN is a mayor annoyance for VHDL designers. For schematics the workaround is to set the "View HDL..." properties to VHDL. For coregen you found out to delete the verilog files, but if I remember it correctly, there may also be a property that can be set to avoid the use of the verilog files.
ISE PN should have a global project property where designers can chose between VHDL, verilog and bilangula flows. And this property should be stored like the other global settings like the chip and the prefered simulator etc.
You need a "midex mode" license for ModelSim if you want to simulate verilog and vhdl code at the same time. This license is not included in your Modelsim XE Xilinx Edition. If you dt want to purchase an apropiate Modelsim Version (10k=80) you have to decide which language you wanna use.