ISERDES strange simulation behaviour

In the Virtex-4 user guide (ug070.pdf p.365 table 8-4) it is clearly indicated that for INTERFACE_TYPE=NETWOKING and DATA_RATE=SDR the latency should be 2 CLKDIV clock periods. I instantiated an ISERDES of DATA_WIDTH=6 but I see that valid output appears on the next CLKDIV rizing edge. Any explanations?

Merci d'avance!

Here is my code:

--------------CUT HERE FILE SERDES_inst.v--------------- module ISERDES_inst(CLK,CLKDIV,D,CE1,SR,REV, Q1,Q2,Q3,Q4,Q5,Q6); // I/O Ports // Inputs input CLK,CLKDIV,D,CE1,SR,REV; // Outputs output Q1,Q2,Q3,Q4,Q5,Q6;

// ISERDES: Source Synchronous Input Deserializer // Virtex-4 // Xilinx HDL Language Template version 8.1i ISERDES #( .BITSLIP_ENABLE("FALSE"), // TRUE/FALSE to enable bitslip controller .DATA_RATE("SDR"), // Specify data rate of "DDR" or "SDR" .DATA_WIDTH(6), // Specify data width - For DDR 4,6,8, or 10 // For SDR 2,3,4,5,6,7, or 8 .INIT_Q1(1'b0), // INIT for Q1 register - 1'b1 or 1'b0 .INIT_Q2(1'b0), // INIT for Q2 register - 1'b1 or 1'b0 .INIT_Q3(1'b0), // INIT for Q3 register - 1'b1 or 1'b0 .INIT_Q4(1'b0), // INIT for Q4 register - 1'b1 or 1'b0 .INTERFACE_TYPE("NETWORKING"), // Use model - "MEMORY" or "NETWORKING" .IOBDELAY("NONE"), // Specify outputs where delay chain will be applied // "NONE", "IBUF", "IFD", or "BOTH" .IOBDELAY_TYPE("DEFAULT"), // Set tap delay "DEFAULT", "FIXED", or "VARIABLE" .IOBDELAY_VALUE(0), // Set initial tap delay to an integer from 0 to 63 .NUM_CE(1), // Define number or clock enables to an integer of 1 or 2 .SERDES_MODE("MASTER"), // Set SERDES mode to "MASTER" or "SLAVE" .SRVAL_Q1(1'b0), // Define Q1 output value upon SR assertion -

1'b1 or 1'b0 .SRVAL_Q2(1'b0), // Define Q2 output value upon SR assertion - 1'b1 or 1'b0 .SRVAL_Q3(1'b0), // Define Q3 output value upon SR assertion - 1'b1 or 1'b0 .SRVAL_Q4(1'b0) // Define Q4 output value upon SR assertion - 1'b1 or 1'b0 ) my_ISERDES_inst ( .O(), // 1-bit combinatorial output .Q1(Q1), // 1-bit registered output .Q2(Q2), // 1-bit registered output .Q3(Q3), // 1-bit registered output .Q4(Q4), // 1-bit registered output .Q5(Q5), // 1-bit registered output .Q6(Q6), // 1-bit registered output .SHIFTOUT1(), // 1-bit carry output .SHIFTOUT2(), // 1-bit carry output .BITSLIP(), // 1-bit Bitslip input .CE1(CE1), // 1-bit clock enable input .CE2(), // 1-bit clock enable input .CLK(CLK), // 1-bit clock input .CLKDIV(CLKDIV), // 1-bit divided clock input .D(D), // 1-bit serial data input .DLYCE(), // 1-bit delay chain enable input .DLYINC(), // 1-bit delay increment/decrement input .DLYRST(), // 1-bit delay chain reset input .OCLK(), // 1-bit high-speed clock input .REV(REV), // 1-bit reverse SR input .SHIFTIN1(), // 1-bit carry input .SHIFTIN2(), // 1-bit carry input .SR(SR) // 1-bit set/reset input ); // End of ISERDES_inst instantiation

endmodule

-------------- END CUT HERE FILE SERDES_inst.v---------------

--------------CUT HERE FILE SERDES_inst_tb.v----------------- `timescale 1ns / 1ps module SERDES_inst_tb;

// Inputs reg CLK,CLKDIV,D,CE1,SR,REV;

// Outputs wire Q1,Q2,Q3,Q4,Q5,Q6;

// Parameters parameter CLK_PERIOD=2.85; parameter CLKDIV_PERIOD=CLK_PERIOD*6;

// Variables integer i=0;

// Instantiate the Unit Under Test (UUT) ISERDES_inst uut ( .CLK(CLK), .CLKDIV(CLKDIV), .D(D), .CE1(CE1), .SR(SR), .REV(REV), .Q1(Q1), .Q2(Q2), .Q3(Q3), .Q4(Q4), .Q5(Q5), .Q6(Q6) ); always #(CLK_PERIOD/2) CLK=~CLK; always #(CLKDIV_PERIOD/2) CLKDIV=~CLKDIV;

initial begin // Initialize Inputs CLK=1; CLKDIV=0; D=0; CE1=0; SR=0; REV=0;

// Wait 100 ns for global reset to finish #100;

// Add stimulus here // Testing availability of REV and the behaviour of SR @(negedge CLKDIV)#(0.5)REV=1; //#(CLKDIV_PERIOD); @(negedge CLKDIV)#(2)REV=0; #(2*CLKDIV_PERIOD); SR=1; #(CLKDIV_PERIOD)/*$stop*/; // Testing the ISERDES main functionality CE1=1; SR=0; @(posedge CLKDIV); @(negedge CLK); for(i=1;i