JTAG CPLD Configuration


I have a Xilinx XCR3064 CPLD with its JTAG pins hooked up to some digital I/O pins on a uC. I intend to configure the CPLD from a binary file held in uC flash by bit-banging the uC pins. So far I've implemented the TAP state machine and managed to correctly read the 32 bit ID code, so a start has been made.

But what to do now? The documentation seems sparse or overwhelming but undetailed.

What I've found so far is:

CoolRunner Programming Algorithm

Enter the device into ISP mode Erase the entire device Program all addresses Verify all addresses Exit the ISP mode and return to normal functional mode.

Which all seems fair enough but insufficient. Do I use the commands isp-write, then clock in the bitstream followed by isp-program? Is there some sort of flag which will tell me when an erase or write has finished?

How do I make the bitstream from an ascii .jed file? Do I just ignore the various markers and bundle the 0's and 1's into a binary file?

These svf and xsvfs files look a bit unnecessary. Is the bitstream loaded in one lump? Is the erase just one command?

All these questions and more; I know many people must have done this but can't find anything clear. I've not used JTAG before, so it's all a bit confusing. I did it years ago with a RAM-based FPGA but that was an easy non-JTAG port method.

There are good technical reasons for not using an FPGA for this which I can't go into.



Keith Wootten
PS.  First time for using Outhouse on newsgroups, so sorry in
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