Jtag CPLD configuration. (2025 Update)

Sep 07, 2007 Last reply: 8 months ago 3 Replies
K
<Previously posted to comp.arch.fpga with no luck so far. Thought I'd try here.>

Hello



I have a Xilinx XCR3064 CPLD with its JTAG pins hooked up to some digital I/O pins on a uC. I intend to configure the CPLD from a binary file held in uC flash by bit-banging the uC pins. So far I've implemented the TAP state machine and managed to correctly read the 32 bit ID code, so a start has been made.



But what to do now? The documentation seems sparse or overwhelming but undetailed.



What I've found so far is:



<quote>

CoolRunner Programming Algorithm



Enter the device into ISP mode Erase the entire device Program all addresses Verify all addresses Exit the ISP mode and return to normal functional mode. </quote>



Which all seems fair enough but insufficient. Do I use the commands isp-write, then clock in the bitstream followed by isp-program? Is there some sort of flag which will tell me when an erase or write has finished?



How do I make the bitstream from an ascii .jed file? Do I just ignore the various markers and bundle the 0's and 1's into a binary file?



These svf and xsvfs files look a bit unnecessary. Is the bitstream loaded in one lump? Is the erase just one command? I saw a reference to blocks, whassat then?



All these questions and more; I know many people must have done this but can't find anything clear. I've not used JTAG before, so it's all a bit confusing. I did it years ago with a RAM-based FPGA but that was an easy non-JTAG port method, 'slave serial mode' IIRC.



There are good technical reasons for not using an FPGA for this which I can't go into.



Help?



TVM


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P

I think you'll find it all in the appnote

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There's a link to a download for the C source of the files required.

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D

The 3064 is the oldest - from the Philips time - Coolrunner. I have the data it takes to be programmed - in fact, I have it supported by my logic compiler under DPS (which probably is of no interest to you since you have no DPS machine). Some of the data took some reverse-engineering from me - I discovered Philips had given me not all fusemap data when it was too late - part designed in, Xilinx having taken over (and talking to Xilinx about fusemap data is a waste of time, unless you need a good laughter - at some point some "support" person told me I had to make a $20M quarterly revenue for them then they would consider my case and perhaps hand me the data...)

You can contact me privately at snipped-for-privacy@tgi-sci.com if you want me to do some digging and send you the files I have, I can do that and will be happy to do it. If you want to use newer - purely Xilinx - coolrunners, I can be of little if any help, though.

Dimiter

------------------------------------------------------ Dimiter Popoff Transgalactic Instruments

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K

required.

Thanks, Paul, I've seen that: it's quite complicated. I had hoped there would be an easier way, after all, I did it years ago with a much bigger FPGA using a serial mode. This is just a

64 macrocell CPLD - surely it must be simpler?

There's a little over 3KB of configuration bits as far as I can tell from the .jed file - do Xilinx/Philips deliberately obscure matters for these parts?

Cheers

Keith Wootten
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