I have a problem width my CPLD-SPI_flash configuration system.
I have made a configuration interface for my Spartan 3 FPGA involving a CPLD (CoolRunner 2) and SPI flash (M25P32).
My FPGA is set up to serial master configuration mode. The FPGA is generating the clock for the CPLD and the CPLD transfers the data from the SPI flash to the DIN pin on the FPGA. I use the application notes and source code xapp800 from Xilinx.
I monitor the CPLD and it steps through states (1-4):1 STATE_RESET 2 LOAD_READ_OPCODE 3 LOAD_READ_ADDRESS 4 READ_DATA 5 WAIT_STATE
The CPLD stays in state 4 where it waits for the FPGA to indicate configuration done by pulling the DONE pin high.
The hardware seams to work. I can see the data on the DIN pin of the FPGA but the FPGA never indicates configuration done by pulling the DONE pin high.
I think the problem may be the process of converting the .bit file to a format that can be written to the serial flash.
Anyone that have any suggestions on how to find the problem?
Andreas Beier Computer Systems Engineer