Hi, I find a problem in the simulation of watchvhd example from Xilinx ISE
8.2 or 9.1. There is a Core generated counter, named xcounter. Even I perform behavioral simulation, its 4-bit output (q) has 2ns delay with its clk. Other (onesout and tensout) have no such problems. For behavioral simulation, I think that it should not have timing delay with clock. What is the problem? Thank you very much.