I am not yet done with my debugging yet, but thought would find out if anyone out has experimented with slave serial configuraiton of Spartan3.
Here is the setup on my PCB board.
The HSWAP_EN is tied to ground. The mode pins are floating. An Atmega128 running at 5V has mapped to it the configuration signal I/O of the FPGA. The PROG_B, INIT, CCLK, DIN. A series resistor(300ohm) is connected between the DIN (FPGA 3.3V)and Atmega128(5V).
I can configure the FPGA from a JTAG port without changing the mode pins.
I configure(via JTAG) the FPGA to run a continuous loop to blink LEDs. Then my Atmega drives the PROG_B signal low, which resets the FPGA. The INIT line is then checked and for some reason(using a Oscope) I have not been able to see the INIT line go low at all.
After checking the INIT line, the atmega drives the CCLK low. The atmega128 reads one byte from the flash and then unpacks each byte and toggles the DIN signal according to the byte.
The sequence for the 8 bits is as follows:
CCLK_LO() toggle DIN(LSB) CCLK_HI() toggleDIN(LSB)
CCLK_LO() toggle DIN(LSB+1) CCLK_HI() toggle_DIN(LSB+1)
and so on.
I have counter which keeps track of the bytes,which is 212393 bytes for a Spartan3XC3S400. After counter expires, I toggle the CCLK a few more time (as said in earlier discussions on this fourum).
I am not sure why the DONE bit is not going high?????
Any ideas?