Webpack sees 2 clocks when there is only one

Hello,

I'm implementing a data bus between a FPGA (XC2S100) and an 8051. Due to the
multiplexed data/address bus I have to latch the 16 bit address on the
falling edge of ALE (before the lower address byte is changed to the data
byte) so I implement the latch easy enough, however when I sythesize it
through the webpack it interprets this as a clock signal and gives me an
error that it is connected to the wrong pin, it states that I should have it
connected to a clock input. My question is how do I get the sythesizer to
overlook this signal as a clock and treat it as a simple input.

Your help would be greatly appreciated.

In case you needed to see the snipit of code that I'm using to latch the
data here it is (note I've also tried using ale_n'event and ale_n = '0'
instead of faling_edge just in case the translation was somewhat messed up).
This process latches the lower address byte into the signal address_low from
the address_data bidirectional port on my entity.

...
process(reset, ale_n) begin
    if reset = '1' then
        address_low    <= (others => '0');
    elsif falling_edge(clk) then
        address_low <= address_data;
    end if;
end process;
...

Thanks

Jason