Hello, I have generated a block-ram based FIFO queue (2 independent clocks, 2 inputs, 1 output) with the use of Core Generator. In the creator I used the
36 bit data bus. Is it possible to parameterize this variable? I think, that the Xilinx doesn't give such possibility. The generated code:
LIBRARY ieee; USE ieee.std_logic_1164.ALL;
-- synthesis translate_off Library XilinxCoreLib;
-- synthesis translate_on ENTITY fifa IS port ( din: IN std_logic_VECTOR(35 downto 0); rd_clk: IN std_logic; rd_en: IN std_logic; rst: IN std_logic; wr_clk: IN std_logic; wr_en: IN std_logic; dout: OUT std_logic_VECTOR(35 downto 0); empty: OUT std_logic; full: OUT std_logic); END fifa;
ARCHITECTURE fifa_a OF fifa IS
-- synthesis translate_off component wrapped_fifa port ( din: IN std_logic_VECTOR(35 downto 0); rd_clk: IN std_logic; rd_en: IN std_logic; rst: IN std_logic; wr_clk: IN std_logic; wr_en: IN std_logic; dout: OUT std_logic_VECTOR(35 downto 0); empty: OUT std_logic; full: OUT std_logic); end component;
-- Configuration specification for all : wrapped_fifa use entity XilinxCoreLib.fifo_generator_v4_1(behavioral) generic map( c_has_int_clk => 0, c_rd_freq => 1, c_wr_response_latency => 1, c_has_srst => 0, c_has_rd_data_count => 0, c_din_width => 36, c_has_wr_data_count => 0, c_full_flags_rst_val => 1, c_implementation_type => 2, c_family => "virtex2p", c_use_embedded_reg => 0, c_has_wr_rst => 0, c_wr_freq => 1, c_underflow_low => 0, c_has_meminit_file => 0, c_has_overflow => 0, c_preload_latency => 1, c_dout_width => 36, c_rd_depth => 1024, c_default_value => "BlankString", c_mif_file_name => "BlankString", c_has_underflow => 0, c_has_rd_rst => 0, c_has_almost_full => 0, c_has_rst => 1, c_data_count_width => 10, c_has_wr_ack => 0, c_use_ecc => 0, c_wr_ack_low => 0, c_common_clock => 0, c_rd_pntr_width => 10, c_use_fwft_data_count => 0, c_has_almost_empty => 0, c_rd_data_count_width => 10, c_enable_rlocs => 0, c_wr_pntr_width => 10, c_overflow_low => 0, c_prog_empty_type => 0, c_optimization_mode => 0, c_wr_data_count_width => 10, c_preload_regs => 0, c_dout_rst_val => "0", c_has_data_count => 0, c_prog_full_thresh_negate_val => 1020, c_wr_depth => 1024, c_prog_empty_thresh_negate_val => 3, c_prog_empty_thresh_assert_val => 2, c_has_valid => 0, c_init_wr_pntr_val => 0, c_prog_full_thresh_assert_val => 1021, c_use_fifo16_flags => 0, c_has_backup => 0, c_valid_low => 0, c_prim_fifo_type => "1kx36", c_count_type => 0, c_prog_full_type => 0, c_memory_type => 1);
-- synthesis translate_on BEGIN
-- synthesis translate_off U0 : wrapped_fifa port map ( din => din, rd_clk => rd_clk, rd_en => rd_en, rst => rst, wr_clk => wr_clk, wr_en => wr_en, dout => dout, empty => empty, full => full);
-- synthesis translate_on
END fifa_a;
There are 2 parameters: c_din_width =>36 and c_dout_width => 36. I can't use here values greater than 36. What is the use of this parameters? Can I change this parameters values to i.e. 20? I would like to use the queue with different sizes of the data bus. Is it a good solution to create a maximum size data bus and use it to write there smaller data? Or maybe it is better to create a 1bit queue, and with the use of GENERATE command generate N 1 bit queues to have a N-bit queue?
Device is Virtex2Pro.
Regards, zlotawy