Hi all,
I am simulating a entity with Modelsim via Xilinx Webpack. Modelsim only displays the input/output signals of the simulated top entity.
Is there a way of viewing the internal signals declared in the architecture of the entity without adding them to the port outputs of the simulated top entity?
Thanks very much
Regards
Joseph
Modelsim will optimise your design by default and hence you might loose some internal signals, try "log -r *" before running your simulation.
Hans
Sorry if this is obvious, but you have tried descending the hierarchy in the "Workspace" window? Signals at the current level are listed in "Objects", & you can add them to the display.
I don't know if this will help you, but I've noticed that the new version of Modelsim optimizes away internal signals by default. I have to use a new argument in vsim:
vsim -voptargs="+acc" test
-Kevin
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