Xilinx SRL16 test

Yes you are right about the 11 cycles.

I don't get any output at all. Zero zolts.

Just to make sure that I wasn't doing a silly mistake with the pin assignments, I ran this code below, which removes the feedback loop, and just feeds through a d input that is connected to a pushbutton. Works fine. There must be something wrong in the original code with either the syntax of the init statement or the initialization and start up after configuration of the Xilinx Spartan 3.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM; use UNISIM.VComponents.all;

entity srltest is port( clk : in std_ulogic; d : in std_logic; q : out std_ulogic ); end srltest;

architecture Behavioral of srltest is

component SRL16 -- synthesis translate_off generic ( INIT: bit_value:= X"1001"); -- synthesis translate_on port (Q : out STD_ULOGIC;

A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; CLK : in STD_ULOGIC; D : in STD_ULOGIC); end component; -- Component Attribute specification for SRL16 -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes in this section -- Component Instantiation for SRL16 should be placed -- in architecture after the begin keyword

-- signal feedback : std_ulogic;

begin

SRL16_INSTANCE_NAME : SRL16 -- synthesis translate_off generic map( INIT => X"7878" ) -- synthesis translate_on port map (Q => q , A0 => '0', A1 => '1', A2 => '0', A3 => '1', CLK => clk, D => d );

-- q

I'm just following the example in the library. I don't get why it says to turn synthesize off. When I take these -- statements out I get errors.

Works now thanks. This code initiates the SRL16 with some sort of pattern, then loops it around continuously in a 10 bit cycle, and outputs to a pad where it can be seen with a scope. Not sure what the translate on/off or generic stuff is all about.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM; use UNISIM.VComponents.all;

entity srltest is port( clk : in std_ulogic; q : out std_ulogic ); end srltest;

architecture Behavioral of srltest is

component SRL16 -- synthesis translate_off generic ( INIT: bit_value:= X"6626"); -- synthesis translate_on port (Q : out STD_ULOGIC;

A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; CLK : in STD_ULOGIC; D : in STD_ULOGIC); end component; -- Component Attribute specification for SRL16 -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes in this section -- Component Instantiation for SRL16 should be placed -- in architecture after the begin keyword

attribute init: string ; attribute init of SRL16_INSTANCE_NAME: label is "6626";

signal feedback : std_logic;

begin

SRL16_INSTANCE_NAME : SRL16 -- synthesis translate_off generic map( INIT => "6626" ) -- synthesis translate_on port map ( Q => feedback, A0 => '1', A1 => '0', A2 => '0', A3 => '1', CLK => clk, D => feedback );

q

Generally speaking (I'll talk about the exceptions in a second), the generic gets the init value passed to the simulator but not to the hardware, and the init attribute passes it to the hardware. So assuming that is the case, you need the init attribute on the primitive in order to pass the initialization to the edif netlist (and thus on to the bit file). The attributes are ignored by simulation, so you need to set the primitive up with a generic in order to initialize the simulation so that it matches the hardware.

About a year ago, some synthesis tools started parsing certain generics like the init generic to automatically pass the generic value to the hardware (essentially by automatically adding an init=attribute), so if you have one of those synthesis tools, you technically do not need to include an init attribute. However, if you want your code portable between tools that do this and tools that don't, then you need to make so the tool ignores the generic when it synthesizes the design. The translate_on/off pragmas are a switch that cause the synthesis to skip over those lines (it you don't then you end up with two inits in the edif which causes problems in the translate in the xilinx tool chain).

The code you have here has the generic, but it is ignored in synthesis so it never gets passed to the bitstream regardless of whether the tool can do it or not. You are missing the matching INIT attribute, which I see you have in one of the follow up posts.

Another th> OK. What is wrong with this code? I am expecting to initiate the SRL16 with

--

--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com

"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

Thanks Ray, that helps a lot.

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