Re: Help with Xilinx Ram16X1S example VHDL code

See below for one potential issue: the synthesis translate_off and translate_on directives should surround the simulation-only portion of the code.

Jason

Hello, > > I have been trying to use distributed ram on a Spartan 3. I get an > error from XST with with this simple example from the docs > > error: > > Analyzing Entity (Architecture ). > ERROR:Xst:764 - E:/data/f100/f100mb/dutyRAM16.vhd line 48: No default > binding for component: . Generic is not on the > entity. > > > > -- This example shows how to create a > -- RAM using xilinx RAM16x1S component. > library IEEE; > use IEEE.std_logic_1164.all; >

-- synthesis translate_off

library UNISIM; > use UNISIM.VComponents.all;

-- synthesis translate_on

> entity myRAM is > port ( > o : out std_logic; > we : in std_logic; > clk : in std_logic; > d : in std_logic; > a0,a1,a2,a3 : in std_logic > ); > end myRAM; > architecture xilinx of myRAM is > component RAM16x1S is > generic (INIT : string := "0000"); > port ( > O : out std_logic; > D : in std_logic; > A3, A2, A1, A0 : in std_logic; > WE, WCLK : in std_logic > ); > end component; > begin > U0 : RAM16x1S > generic map (INIT => "FFFF") > port map (O => o, WE => we, WCLK => clk, D => d, > A0 => a0, A1 => a1, A2 => a2, A3 => a3); > > end xilinx; > > -------------------------------------------------------------------- > > > Am I missing something? > > Thanks > > Patrick >
Reply to
jtw
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This is old advice and actually, I would suggest you do not isolate the INITs with translate_off/translate_on's if you are using a recent version of XST or Synplicity (do not know about Mentor or Synopsys). By not using the synthesis translate function, the same INIT values will be used for both synthesis and simulation. Otherwise, you would need to specify them twice and have the more likely chance of getting them out of sync with each other plus the fact that you will write more lines of code to do the same thing.

I think this problem likely stemmed from the fact the INIT was declared as a string in the component decalaration as Paulo identified which would cause binding errors in simulation as well as synthesis so using translate_off would not have corrected the problem. The INIT should have been decalred as a bit_vector. What would have been probably even better is to just not declare the component declaration at all and instead just let the:

library UNISIM; use UNISIM.VComponents.all;

bind the component. Again in the recent versions of the synthesis tools, you do not need to isolate the library declaration using translate_on/off's and it will use it in order to properly bind the components. This makes for cleaner code in my opinion and limits the possibility of encountering issues like this one.

-- Brian

Reply to
Brian Philofsky

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