See below for one potential issue: the synthesis translate_off and translate_on directives should surround the simulation-only portion of the code.
Jason
Hello,
>
> I have been trying to use distributed ram on a Spartan 3. I get an
> error from XST with with this simple example from the docs
>
> error:
>
> Analyzing Entity (Architecture ).
> ERROR:Xst:764 - E:/data/f100/f100mb/dutyRAM16.vhd line 48: No default
> binding for component: . Generic is not on the
> entity.
>
>
>
> -- This example shows how to create a
> -- RAM using xilinx RAM16x1S component.
> library IEEE;
> use IEEE.std_logic_1164.all;
>
-- synthesis translate_off
library UNISIM;
> use UNISIM.VComponents.all;
-- synthesis translate_on
> entity myRAM is
> port (
> o : out std_logic;
> we : in std_logic;
> clk : in std_logic;
> d : in std_logic;
> a0,a1,a2,a3 : in std_logic
> );
> end myRAM;
> architecture xilinx of myRAM is
> component RAM16x1S is
> generic (INIT : string := "0000");
> port (
> O : out std_logic;
> D : in std_logic;
> A3, A2, A1, A0 : in std_logic;
> WE, WCLK : in std_logic
> );
> end component;
> begin
> U0 : RAM16x1S
> generic map (INIT => "FFFF")
> port map (O => o, WE => we, WCLK => clk, D => d,
> A0 => a0, A1 => a1, A2 => a2, A3 => a3);
>
> end xilinx;
>
> --------------------------------------------------------------------
>
>
> Am I missing something?
>
> Thanks
>
> Patrick
>