Works now thanks. This code initiates the SRL16 with some sort of pattern, then loops it around continuously in a 10 bit cycle, and outputs to a pad where it can be seen with a scope. Not sure what the translate on/off or generic stuff is all about.
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM; use UNISIM.VComponents.all;
entity srltest is port( clk : in std_ulogic; q : out std_ulogic ); end srltest;
architecture Behavioral of srltest is
component SRL16 -- synthesis translate_off generic ( INIT: bit_value:= X"6626"); -- synthesis translate_on port (Q : out STD_ULOGIC;
A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; CLK : in STD_ULOGIC; D : in STD_ULOGIC); end component; -- Component Attribute specification for SRL16 -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes in this section -- Component Instantiation for SRL16 should be placed -- in architecture after the begin keyword
attribute init: string ; attribute init of SRL16_INSTANCE_NAME: label is "6626";
signal feedback : std_logic;
begin
SRL16_INSTANCE_NAME : SRL16 -- synthesis translate_off generic map( INIT => "6626" ) -- synthesis translate_on port map ( Q => feedback, A0 => '1', A1 => '0', A2 => '0', A3 => '1', CLK => clk, D => feedback );
q