Under the sim tab in the workspace box, a complete design hierarchy is present. You can browse through all of your sub-modules. If you want to add all signals for a sub-module into the wave you can simply drag the sub module. Otherwise, you can click on the sub-module and lookin the objects pane. It has all of the signals in that module. You can select all of the signals you want to add by ctrl+clicking each of them, then you can add them to the wave by going to add menu -> wave ->
selected signals. Also, you can drag the signals from the objects pane straight to the wave window.
Yes you can save the waveform settings. You click the save button while the waveform pane is selected. It saves to a .do file. A .do file is just a script file that you can run when you want to restore those settings. It's not automatic, but next time you load the project you can type in the console do wave.do (or whatever you saved it as).
No you don't have to close Modelsim everytime you resynthesize. You just need to recompile (by going to the project tab of the workspace and right clicking and choosing the appropriate compile command) and then restart the simulation.
I hope that helped (though it appears other people have replied already)
my problem is that behavior simulation doesnt work somehow. Therefore I have to do post-translate simulation. However during translation XST doesnt keep the net-names, so its a little bit hard to find the right net in modelsim, I don't even know which net to take. Do I have to pick the right net using fpga-editor? Or how do I get an overview over the new nets?
Why ? Understand what doesn't work and fix it ! Don't synthesize RTL code which doesn't even simulate... Do you hope synthesis will miraculously "fix" a bad description ? The usual question is : "my RTL works (simulates ok) but the chip doesn't".
I knew it was not for a good reason.
It's not a translation. It's synthesis. XST infers physical hardware on which it tries to map the behavior you've described in RTL. Garbage in -> Garbage out.
You should do as suggested by all the experienced designers :
- Learn synchronous design.
- Make sure you understand how VHDL works.
- Write good quality RTL, follow the rules mentioned.
- Make a very quick synthesis pass to uncover usual mistakes Focus on reports, warnings, and chase down words like "asynchronous", "combinational" "feedback" "loop" "latch" etc...
- Write good (reliable, self testing, documented, reuseable...) test benches.
- Simulate carefully the RTL code
- Do a careful synthesis
- If the design is challenging timing-wise, do a unitary P&R and verify the actual timing figures with Static Timing Analysis.
There is usually no need to perform timing sim, for reasons outside the scope of this post (and for the complexity level you are targeting).
A little time spent with the tools' documentation is a good investment.
Analyze known good code and understand how the design it was implemented and why. Re-inventing the wheel has its virtues, but it takes time... And no : don't open ISE's JC VHDL examples projects ;-)
Modelsim has really bad error messages. The error message you got is a catch all error message :-). In all probability there is small mistake in syntax or settings.
1) One does not instantiate a test bench. Test bench is a place holder for your enitity under test and logic required to test the entity. "My testbench is instantiated as uut." did you mean that you have named your testbench as "uut"?
2) Did your test bench compile without any errors?
Post-Translate Simulation works. However Behavioral Model simulation still doesn't.
my testbench is instantiated like this: ... -- Instantiate the Unit Under Test (UUT) uut: led_test PORT MAP( ... Under properties in the Project Navigator I have entered UUT as instance name. (it works for the other types of simulation).
since I have inserted a SRL16, it hangs now SRL16_inst : SRL16 generic map ( INIT => X"0000") port map ( Q => dcm3_rst, -- SRL data output A0 => '1', -- Select input A1 => '1', -- Select input A2 => '0', -- Select input A3 => '0', -- Select input CLK => clk_ibufg, -- Clock input D => not lvds_locked -- SRL data input );