Hi all,
I'm using the code below to generate a pulse which is 16x57600 from a
51.2 MHz clock signal to controll the sampling in a rs232 module. The pulse generator does not work however. It generats a constant high signal instead of a 921.6 kHz pulse.Can anyone see what might be faulty with my design? I'm clueless...
/Johan
library IEEE; use IEEE.std_logic_1164.all;
library unisim; use unisim.vcomponents.all;
entity baud16 is port( Clk : in std_logic; baud_pulse : out std_logic); end entity baud16;
architecture imp of baud16 is
attribute BOX_TYPE : string; component SRL16E is -- synthesis translate_off generic ( INIT : bit_vector := X"0000" ); -- synthesis translate_on port ( CE : in std_logic; D : in std_logic; Clk : in std_logic; A0 : in std_logic; A1 : in std_logic; A2 : in std_logic; A3 : in std_logic; Q : out std_logic ); end component SRL16E; attribute BOX_TYPE of SRL16E : component is "BLACK_BOX"; component FD is port ( C : in std_logic; D : in std_logic; Q : out std_logic); end component FD; attribute BOX_TYPE of FD : component is "BLACK_BOX";
signal clkdv56 : std_logic; signal clkdv56_i1 : std_logic; signal clkdv56_i2 : std_logic; signal clkdv56_i3 : std_logic;
-- signal clkdv14_4 : std_logic; signal baud_pulse_i : std_logic; begin
--Denna SRL dividerar inklockan med 14 Del_8 : SRL16E --synthesis translate_off generic map ( INIT => X"0000") --synthesis translate_on port map ( CE => '1', -- [in std_logic] D => clkdv56, -- [in std_logic] Clk => Clk, -- [in std_logic] A0 => '1', -- [in std_logic] A1 => '1', -- [in std_logic] A2 => '1', -- [in std_logic] A3 => '0', -- [in std_logic] Q => clkdv56_i1); -- [out std_logic]
Del_16_1 : SRL16E --synthesis translate_off generic map ( INIT => X"0000") --synthesis translate_on port map ( CE => '1', -- [in std_logic] D => clkdv56_i1, -- [in std_logic] Clk => Clk, -- [in std_logic] A0 => '1', -- [in std_logic] A1 => '1', -- [in std_logic] A2 => '1', -- [in std_logic] A3 => '1', -- [in std_logic] Q => clkdv56_i2); -- [out std_logic]
Del_16_2 : SRL16E --synthesis translate_off generic map ( INIT => X"0000") --synthesis translate_on port map ( CE => '1', -- [in std_logic] D => clkdv56_i2, -- [in std_logic] Clk => Clk, -- [in std_logic] A0 => '1', -- [in std_logic] A1 => '1', -- [in std_logic] A2 => '1', -- [in std_logic] A3 => '1', -- [in std_logic] Q => clkdv56_i3); -- [out std_logic]
Del_16_3 : SRL16E --synthesis translate_off generic map ( INIT => X"0001") --synthesis translate_on port map ( CE => '1', -- [in std_logic] D => clkdv56_i3, -- [in std_logic] Clk => Clk, -- [in std_logic] A0 => '1', -- [in std_logic] A1 => '1', -- [in std_logic] A2 => '1', -- [in std_logic] A3 => '1', -- [in std_logic] Q => clkdv56); -- [out std_logic]
DFF : FD port map ( C => Clk, -- [in std_logic] D => clkdv56, -- [in std_logic] Q => baud_pulse); -- [out std_logic]
end architecture imp;