is this memory implementation synthesizeable?

Question

Hi allI have implemented a very easy memory with a few registers, where i canstore and also read values for and from my ALU:I have got 2 questions:1) The conv_integer procedure does not work here, I always get theerrormessage: no feasable subprogram entry for conv_integer. Any ideas whats wrong here?2) Finally this memory should be synthizeable for a Xilinx ML300 board. Whatdo I have to change that this will be alright?Is there a documention available? I wasnt able to find one online, which says me in a detailed way what constructs I can use!Thanks for any useful hintsSDlibrary ieee;use use use entity memory is generic (width : integer := 32); port (clk : in std_ulogic;       rst : in std_ulogic;        inp : in std_ulogic_vector((2*width-1) downto 0);         addr: in std_ulogic_vector(3 downto 0);          wr  : in std_ulogic;           rd  : in std_ulogic;           outp: out std_ulogic_vector((2*width-1) downto 0)      );end memory;architecture rtl of memory is   type reg_type is array (0 to 3) of std_ulogic_vector((2*width-1) downto0);   signal reg_file : reg_type;beginwrite : process(clk,rst,inp,addr,wr)variable x_int : integer;begin  if rst = '1' then     reg_file(0)  '0');  else     if clk'event and clk = '1' then       if wr = '1' then         reg_file(conv_integer(addr))

Tim · Accepted Answer

"Stefan Duenser" wroteOn this one,  is the place for the VHDL questions.If you check the archive you will see a zillion repetitions ofthis advice:  use the numeric_std libraryThen you can use to_integer().I usually use an indirect function to clean up the simulation:    library IEEE;    use     use     function ToInteger(ARG: UNSIGNED) return INTEGER is      variable x: unsigned(ARG'range);      variable n: integer;    begin      x := ARG;      -- synthesis translate_off      for i in x'range loop        if x(i)/='1' then       -- resolve the 'undefined' signals          x(i) := '0';        end if;      end loop;      -- synthesis translate_on      n := to_integer(x);      return n;    end;

Stefan Duenser · Answer

I really dont understand why this is not working, because this functions are declared in the ieee.std_logic_arith.all header...

FUNCTION to_integer ( arg1 : STD_ULOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER; FUNCTION to_integer ( arg1 : STD_LOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER; FUNCTION to_integer ( arg1 : STD_LOGIC; x : INTEGER := 0 ) RETURN NATURAL; FUNCTION to_integer ( arg1 : UNSIGNED; x : INTEGER := 0 ) RETURN NATURAL; FUNCTION to_integer ( arg1 : SIGNED; x : INTEGER := 0 ) RETURN INTEGER;

FUNCTION conv_integer ( arg1 : STD_ULOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER; FUNCTION conv_integer ( arg1 : STD_LOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER; FUNCTION conv_integer ( arg1 : STD_LOGIC; x : INTEGER := 0 ) RETURN NATURAL; FUNCTION conv_integer ( arg1 : UNSIGNED; x : INTEGER := 0 ) RETURN NATURAL; FUNCTION conv_integer ( arg1 : SIGNED; x : INTEGER := 0 ) RETURN INTEGER

any useful tips?

Jonathan Bromley · Answer

[snip]Take heed of what the nice man said:  USE NUMERIC_STD.Like many other people, you have unnecessarily includedboth  use and  use I think one of the Xilinx tools tends to add both these clauses by default - silly thing to do.Your problem is caused because CONV_INTEGER() is defined in BOTH packages.  Consequently, neitherdefinition is visible.  You could, if you weredesperate, use a fully-qualified function name:  int

is this memory implementation synthesizeable?

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