Before I tried to put the OPB master port to my custom coprocessor, I did the following simple test: MB1 MB2 | | FSL FSL (Master and slave) (master and slave) | |
----------------------------------------------------------------------------- Cutom Coprocessor
So my cutom coprocessor will have two FSL links with each connected to MB1 and MB2. Becasue creat/import peripheral wizard only supports one link, I did the following manually, In my CustomIP core, I declare: entity CustomIP is port ( -- Contact with MB0 MB0_FSL_Clk : in std_logic; MB0_FSL_Rst : in std_logic; MB0_FSL_S_Clk : out std_logic; MB0_FSL_S_Read : out std_logic; MB0_FSL_S_Data : in std_logic_vector(0 to 31); MB0_FSL_S_Control : in std_logic; MB0_FSL_S_Exists : in std_logic; MB0_FSL_M_Clk : out std_logic; MB0_FSL_M_Write : out std_logic; MB0_FSL_M_Data : out std_logic_vector(0 to 31); MB0_FSL_M_Control : out std_logic; MB0_FSL_M_Full : in std_logic; -- Contact with MB1 MB1_FSL_Clk : in std_logic; MB1_FSL_Rst : in std_logic; MB1_FSL_S_Clk : out std_logic; MB1_FSL_S_Read : out std_logic; MB1_FSL_S_Data : in std_logic_vector(0 to 31); MB1_FSL_S_Control : in std_logic; MB1_FSL_S_Exists : in std_logic; MB1_FSL_M_Clk : out std_logic; MB1_FSL_M_Write : out std_logic; MB1_FSL_M_Data : out std_logic_vector(0 to 31); MB1_FSL_M_Control : out std_logic; MB1_FSL_M_Full : in std_logic );
attribute SIGIS : string; attribute SIGIS of MB0_FSL_Clk, MB1_FSL_Clk : signal is "Clk"; attribute SIGIS of MB0_FSL_S_Clk, MB1_FSL_S_Clk : signal is "Clk"; attribute SIGIS of MB0_FSL_M_Clk, MB1_FSL_M_Clk : signal is "Clk";
end CustomIP; {.......}
And in the .mpd file, I declared: BEGIN CustomIP
## Peripheral Options ##OPTION IPTYPE = PERIPHERAL OPTION IMP_NETLIST = TRUE OPTION HDL = VHDL OPTION CORE_STATE = ACTIVE OPTION IP_GROUP = MICROBLAZE:PPC:USER
## Bus Interfaces BUS_INTERFACE BUS = M0SFSL, BUS_TYPE = SLAVE, BUS_STD = FSL BUS_INTERFACE BUS = M0MFSL, BUS_TYPE = MASTER, BUS_STD = FSL BUS_INTERFACE BUS = M1SFSL, BUS_TYPE = SLAVE, BUS_STD = FSL BUS_INTERFACE BUS = M1MFSL, BUS_TYPE = MASTER, BUS_STD = FSL
## Generics for VHDL or Parameters for Verilog
## Ports PORT M0FSL_Clk = "", DIR = I, SIGIS = Clk, BUS = M0SFSL:M0MFSL PORT M0FSL_Rst = OPB_Rst, DIR = I, BUS = M0SFSL:M0MFSL PORT M0FSL_S_Clk = FSL_S_Clk, DIR = O, SIGIS = Clk, BUS = M0SFSL PORT M0FSL_S_Read = FSL_S_Read, DIR = O, BUS = M0SFSL PORT M0FSL_S_Data = FSL_S_Data, DIR = I, VEC = [0:31], BUS = M0SFSL PORT M0FSL_S_Control = FSL_S_Control, DIR = I, BUS = M0SFSL PORT M0FSL_S_Exists = FSL_S_Exists, DIR = I, BUS = M0SFSL PORT M0FSL_M_Clk = FSL_M_Clk, DIR = O, SIGIS = Clk, BUS = M0MFSL PORT M0FSL_M_Write = FSL_M_Write, DIR = O, BUS = M0MFSL PORT M0FSL_M_Data = FSL_M_Data, DIR = O, VEC = [0:31], BUS = M0MFSL PORT M0FSL_M_Control = FSL_M_Control, DIR = O, BUS = M0MFSL PORT M0FSL_M_Full = FSL_M_Full, DIR = I, BUS = M0MFSL
PORT M1FSL_Clk = "", DIR = I, SIGIS = Clk, BUS = M1SFSL:M1MFSL PORT M1FSL_Rst = OPB_Rst, DIR = I, BUS = M1SFSL:M1MFSL PORT M1FSL_S_Clk = FSL_S_Clk, DIR = O, SIGIS = Clk, BUS = M1SFSL PORT M1FSL_S_Read = FSL_S_Read, DIR = O, BUS = M1SFSL PORT M1FSL_S_Data = FSL_S_Data, DIR = I, VEC = [0:31], BUS = M1SFSL PORT M1FSL_S_Control = FSL_S_Control, DIR = I, BUS = M1SFSL PORT M1FSL_S_Exists = FSL_S_Exists, DIR = I, BUS = M1SFSL PORT M1FSL_M_Clk = FSL_M_Clk, DIR = O, SIGIS = Clk, BUS = M1MFSL PORT M1FSL_M_Write = FSL_M_Write, DIR = O, BUS = M1MFSL PORT M1FSL_M_Data = FSL_M_Data, DIR = O, VEC = [0:31], BUS = M1MFSL PORT M1FSL_M_Control = FSL_M_Control, DIR = O, BUS = M1MFSL PORT M1FSL_M_Full = FSL_M_Full, DIR = I, BUS = M1MFSL END
I hope this will work. But it seems that I have to import it for the CustomIP visible to the XPS project. So I imported it by telling the system the .mpd file and the source .vhd file and choose no link(OPB, FSL, PLB....). Then when I tried to declare my connection in system.mhs file, the system give me the error that there is no interface M1MFSL, M1SFSL, M0MFSL, M0SFSL as I expected. Also the CustomIP which was imported in the system show "encrpted source" and won't show my source .vhd file. Do I miss somthing here? Would you please give me some suggestion or what document should I read?
Thank you so much.