How to make Customized IP which connected with Microblaze through FSL access the OPB bus?

I build a system which has a MicroBlaze, a LMB connect BRAM for local instruction/data memory (8KB) and an OPB connected BRAM(64K) which will be used as a shared memory for the Microblaze my user defined coprocessor.

I connected my coprocessor with the MicroBlaze through FSL by using the tool edit/import peripherals, but how can I make it to access the OPB connected BRAM(64K). Do I have to write all the OPB ports manually in the VHDL file in my coprocessor?

Thank you very much for your help.

Reply to
fpga
Loading thread data ...

FSL links are connected to MB core and can not access the OPB the OPB_MCH_SDRAM IP core has slave FSL ports so external FSL (XCL) master can access the SDRAM over FSL (but not the rest of OPB bus)

so you have options

1) MB software will read FSL and translate it to OPB transaction in software 2) you write your own FSL 2 OPB (master) bridge 3) if you want to access BRAM then you can access the second port of the BRAMs but its rew BRAM port not FSL

Antti

Reply to
Antti

FSL links are connected to MB core and can not access the OPB the OPB_MCH_SDRAM IP core has slave FSL ports so external FSL (XCL) master can access the SDRAM over FSL (but not the rest of OPB bus)

so you have options

1) MB software will read FSL and translate it to OPB transaction in software 2) you write your own FSL 2 OPB (master) bridge 3) if you want to access BRAM then you can access the second port of the BRAMs but its rew BRAM port not FSL

Antti

Reply to
Antti

Hi,

another option is to develop a FSL coprocessor with OPB Master interface (or an OPB Master IP with FSL interface) , isn't it?

Regards,

Ivan

Antti wrote:

Reply to
Ivan

I want my coprocessor can access the BRAM diretly because there is a lot data transfer between them. It will be very unefficient to send these data back to MB through FSL and then put them into OPB RAM or vise verso. I don't want to put connected my coprocessor to the sceond port of the BRAM either because the BRAM(64K) is shared between the MB and my coprocessor and I want the OPB arbitrator to solve the contension problem for me. Then I needn't program my own. For the second choice, write my own FSL2OPB bridge, or as said by ivan: "develop a FSL coprocessor with OPB Master interface" will be quite time consuming because I need to take care of my customized circuit to the OPB bus signals? But it seems the only choice I have. Did I understand this correct?

Thank you very much for all the replies.

Reply to
fpga

yes. if you want to use EDK OPB arbiter then you need your own IP that has OPB master port, and that may be time consumint to develop/troubleshoot

Antti

Reply to
Antti

Hi again,

another possibility (that I have implemented sometime ago) is to use a BRAM memory in the coprocessor. The MB write/read data from this memory through the FSL interface, being accessible for the coprocessor too.

An schematic:

MB BRAM Coprocessor

I hope that it is useful for you.

Ivan

fpga wrote:

Reply to
Ivan

Hello, Ivan:

In your case, how do you deal with the contension when MB and the Coprocessor to the BRAM? And I don't understand why do you use FSL interface to connect the BRAM but not OPB? Thank you very much for your help. I want to build a system as the following. So the OPB arbitrator can deal with the contension when both MB and Coprocessor access the same address in BRAM at same time. MB(M1)FSL InterfaceCoprocessor(M2) | | | | |---OPB(with arbitrator)-----------|----------------->BRAM

Reply to
fpga

Hi,

I used one "BRAM memory" to write data from MB (PORT A) to coprocessor (PORT B) and another to write data from the coprocessor (PORT A) to MB (PORT B).

If you need to share data from BRAM, you can use the OPB bus (as you propose). However, FSL is faster than OPB, and if you only need to share data between the MB and the coprocessor, this solution is more efficient. Of course, you need to develop the "FSL-BRAM interfaces" and the "BRAM-Coprocessor interfaces".

Each approach is correct, it depends of your performance/operation requirements.

Regards,

Ivan

Reply to
Ivan

Before I tried to put the OPB master port to my custom coprocessor, I did the following simple test: MB1 MB2 | | FSL FSL (Master and slave) (master and slave) | |

----------------------------------------------------------------------------- Cutom Coprocessor

So my cutom coprocessor will have two FSL links with each connected to MB1 and MB2. Becasue creat/import peripheral wizard only supports one link, I did the following manually, In my CustomIP core, I declare: entity CustomIP is port ( -- Contact with MB0 MB0_FSL_Clk : in std_logic; MB0_FSL_Rst : in std_logic; MB0_FSL_S_Clk : out std_logic; MB0_FSL_S_Read : out std_logic; MB0_FSL_S_Data : in std_logic_vector(0 to 31); MB0_FSL_S_Control : in std_logic; MB0_FSL_S_Exists : in std_logic; MB0_FSL_M_Clk : out std_logic; MB0_FSL_M_Write : out std_logic; MB0_FSL_M_Data : out std_logic_vector(0 to 31); MB0_FSL_M_Control : out std_logic; MB0_FSL_M_Full : in std_logic; -- Contact with MB1 MB1_FSL_Clk : in std_logic; MB1_FSL_Rst : in std_logic; MB1_FSL_S_Clk : out std_logic; MB1_FSL_S_Read : out std_logic; MB1_FSL_S_Data : in std_logic_vector(0 to 31); MB1_FSL_S_Control : in std_logic; MB1_FSL_S_Exists : in std_logic; MB1_FSL_M_Clk : out std_logic; MB1_FSL_M_Write : out std_logic; MB1_FSL_M_Data : out std_logic_vector(0 to 31); MB1_FSL_M_Control : out std_logic; MB1_FSL_M_Full : in std_logic );

attribute SIGIS : string; attribute SIGIS of MB0_FSL_Clk, MB1_FSL_Clk : signal is "Clk"; attribute SIGIS of MB0_FSL_S_Clk, MB1_FSL_S_Clk : signal is "Clk"; attribute SIGIS of MB0_FSL_M_Clk, MB1_FSL_M_Clk : signal is "Clk";

end CustomIP; {.......}

And in the .mpd file, I declared: BEGIN CustomIP

## Peripheral Options ##OPTION IPTYPE = PERIPHERAL OPTION IMP_NETLIST = TRUE OPTION HDL = VHDL OPTION CORE_STATE = ACTIVE OPTION IP_GROUP = MICROBLAZE:PPC:USER

## Bus Interfaces BUS_INTERFACE BUS = M0SFSL, BUS_TYPE = SLAVE, BUS_STD = FSL BUS_INTERFACE BUS = M0MFSL, BUS_TYPE = MASTER, BUS_STD = FSL BUS_INTERFACE BUS = M1SFSL, BUS_TYPE = SLAVE, BUS_STD = FSL BUS_INTERFACE BUS = M1MFSL, BUS_TYPE = MASTER, BUS_STD = FSL

## Generics for VHDL or Parameters for Verilog

## Ports PORT M0FSL_Clk = "", DIR = I, SIGIS = Clk, BUS = M0SFSL:M0MFSL PORT M0FSL_Rst = OPB_Rst, DIR = I, BUS = M0SFSL:M0MFSL PORT M0FSL_S_Clk = FSL_S_Clk, DIR = O, SIGIS = Clk, BUS = M0SFSL PORT M0FSL_S_Read = FSL_S_Read, DIR = O, BUS = M0SFSL PORT M0FSL_S_Data = FSL_S_Data, DIR = I, VEC = [0:31], BUS = M0SFSL PORT M0FSL_S_Control = FSL_S_Control, DIR = I, BUS = M0SFSL PORT M0FSL_S_Exists = FSL_S_Exists, DIR = I, BUS = M0SFSL PORT M0FSL_M_Clk = FSL_M_Clk, DIR = O, SIGIS = Clk, BUS = M0MFSL PORT M0FSL_M_Write = FSL_M_Write, DIR = O, BUS = M0MFSL PORT M0FSL_M_Data = FSL_M_Data, DIR = O, VEC = [0:31], BUS = M0MFSL PORT M0FSL_M_Control = FSL_M_Control, DIR = O, BUS = M0MFSL PORT M0FSL_M_Full = FSL_M_Full, DIR = I, BUS = M0MFSL

PORT M1FSL_Clk = "", DIR = I, SIGIS = Clk, BUS = M1SFSL:M1MFSL PORT M1FSL_Rst = OPB_Rst, DIR = I, BUS = M1SFSL:M1MFSL PORT M1FSL_S_Clk = FSL_S_Clk, DIR = O, SIGIS = Clk, BUS = M1SFSL PORT M1FSL_S_Read = FSL_S_Read, DIR = O, BUS = M1SFSL PORT M1FSL_S_Data = FSL_S_Data, DIR = I, VEC = [0:31], BUS = M1SFSL PORT M1FSL_S_Control = FSL_S_Control, DIR = I, BUS = M1SFSL PORT M1FSL_S_Exists = FSL_S_Exists, DIR = I, BUS = M1SFSL PORT M1FSL_M_Clk = FSL_M_Clk, DIR = O, SIGIS = Clk, BUS = M1MFSL PORT M1FSL_M_Write = FSL_M_Write, DIR = O, BUS = M1MFSL PORT M1FSL_M_Data = FSL_M_Data, DIR = O, VEC = [0:31], BUS = M1MFSL PORT M1FSL_M_Control = FSL_M_Control, DIR = O, BUS = M1MFSL PORT M1FSL_M_Full = FSL_M_Full, DIR = I, BUS = M1MFSL END

I hope this will work. But it seems that I have to import it for the CustomIP visible to the XPS project. So I imported it by telling the system the .mpd file and the source .vhd file and choose no link(OPB, FSL, PLB....). Then when I tried to declare my connection in system.mhs file, the system give me the error that there is no interface M1MFSL, M1SFSL, M0MFSL, M0SFSL as I expected. Also the CustomIP which was imported in the system show "encrpted source" and won't show my source .vhd file. Do I miss somthing here? Would you please give me some suggestion or what document should I read?

Thank you so much.

Reply to
fpga

I am so sorry about the figure, here it is: MB1 MB2 | | FSL FSL (master and slave) (master and slave) | |

--------------------------------------------------------- Custom IP

Reply to
fpga

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.