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How to develop custom opb devices for Microblaze?

Folks,

I have an EDK(*1) based project that utilizes the Microblaze, along with several peripherals connected via OPB (on-chip peripheral bus) for use with a Spartan3(*2). The project is set to use VHDL. I would like to develop a custom data encoder(*3) Verilog module that can be accessed via C, and I am trying to determine if developing the module as device that attaches to the OPB would be a good choice of implementation. Probably I am missing some important technical considerations about the verilog module's interfaces, etc. However, it appears that if I try to develop the lzw_opb in this fashion, it will require that I write a device driver similar to the other OPB components. Also since the project is set for VHDL, I am not certain how to develop the Verilog project along side. Wondering if anyone else has had a similar issue and can perhaps shed some light on how to approach this kind of problem?

The basic design I have in mind is as follows:

Data Input => UART => C code running on uBlaze => updates state of lzw_opb => UART => Data out

Thanks, BEA

*1 Using Xilinx EDK 6.3 Build EDK_Gmm.12.3+1 *2 Spartan3 xc3s400 *3 LZW compression algo
Reply to
beagle197
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There's a Xilinx IP block called opb_ipif (IP interface) specifically for this. If you're using XPS there's a wizard to make IP blocks and one of the steps will offer to drag one of these in for you.

The OBP BRAM block is just a thin layer between a BRAM and an opb_ipif, for example.

--
Ben Jackson AD7GD

http://www.ben.com/
Reply to
Ben Jackson

You may develop your OPB device without giving a monet thoguht to driver: if you don't provide one, EDK will use "generic" for it.

You may use OPB_IPIF as base design, but I have had no problem in designing my own devices directly connected to OPB, and they usually are more efficient.

I don´t remember if MB in EDK 6.3 had FSL links, they are a nice alternative for some applications.

Best regards,

Zara

Reply to
Zara

If you planning to do some SW acceleration I would advice to use the FSL interface on MicroBlaze instead. There are drivers for handling FSL communication with EDK and you will most likely have a more performance by using FSL instead of OPB.

Göran

Reply to
Göran Bilski

Folks,

The FSL_V20 design is implemented in VHDL, how can I develop my code in Verilog and still be able to interface to the existing FSL device?

Thanks BEA

G=F6ran Bilski wrote:

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Reply to
beagle197

The bus is implemented in VHDL but you don't need to write a new bus.

Just create a new IP under pcores who will interface to the FSL bus. Connect the new IP to a FSL bus in the .mhs file.

Göran

The FSL_V20 design is implemented in VHDL, how can I develop my code in Verilog and still be able to interface to the existing FSL device?

Thanks BEA

Göran Bilski wrote:

Reply to
Göran Bilski

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