multiprocessing with microblaze ?

Hello Stuart,

If you use a good DDR DRAM controller, ie. not the standard one supplied by Xilinx, it gives resonably good performance, especially if you can squeeze in a cache on the instruction and/or data ports. I've made such a controller, which can have up to four ports and running the DDR memory at

133 MHz at 16 bit width (peak bandwidth is thus 2*133*2=532 Mbytes/s) The memory sits on a module with a 1000 kgate Spartan-3 together with 8 MB of flash for FPGA and other data. It can run linux. Write me personally if you'd like more info.

What's your application anyway - you might be better off implementing any heavy duty algorithms using the fpga-logic itself, if you know what I mean.

Regards,

Finn Nielsen snipped-for-privacy@tiscali.dk

We are working with multi CPU microblaze systems - it worksd pretty much as expected under current EDK tools.

Technically it's easy, just design it in EDK and off you go.

But... if you hang 8 MicroBlazes off the OPB connecting to OPB_DDR controller, they'll spend a lot of time waiting on the bus for memory read/write. Caches help of course, but BRAM is a precious commodity.

The new multichannel controller (mch_opb_sdram) and CacheLink interfaces get memory accesses off the OPB bus, but you are limited in how many separate memory ports you get (4), and thus how many CPUs can share that memory (2 CPUs, one channel each for I and D).

Regardless of which you choose, there's no coherency between the CPU caches. This requires some thought if you are using the shared memory for interprocessor communications.

Interesting stuff, and microblaze + EDK is a nice platform for experimentation.

Regards,

John