Microblaze interrupts


I am using a Virtex2 device with a DSP core, written in VHDL and a Microblaze.

The Microblaze has as peripherals a UART, SPI, GPIO, interrupt controller (INTC), external memory controller (EMC), instruction cache , user IP-IF and a Watchdog/Timer (WDT) core.

All peripherals are connected via the OPB to the Microblaze.

Now, the problem.

The interrupt controller has 5 input lines (priority 1 to 5).

When the interrupt handler on the microblaze is called it disables all lower priority interrups by clearing the IER (interrupt enable register) in the INTC. This is for my understanding the way to realize interrupts with different priorities, to allow higher priority interrupts to interrupt lower priority interrupts.

That works. But the great problem is that all lower priority interrupts which occure during a higher priority interrupt is serviced (low prio interrupt enable bit is cleared in the INTC) will be discarded by the INTC, thus not serviced, after the high prio interrupt is finished.

I think there is a "bug" in the INTC, because my interpretation of the docu is that the status register (ISR) will register all incoming interrupts.

All my communiction (UART / SPI) is interrupt driver. And therefore losing interrupts leads to a broken communiction, which is very bad :(.

If the watchdog timer interrupt is lost the system reboots, which is very very bad :(.

Has anybody of you recognized similar problems? How do you used a microblaze with interrupt controller? Does anybody share my opinion of that interrupt controller "bug"?

Thank you very much for your help, Reiner Abl

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Reiner Abl
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