IO Timing constraints with internal clocks

Howdy Håkon,

The short answer is that I'm not aware of a _good_ way to specify it the way that you have described. In fact, some older (but not very old!) FPGAs chips won't even let you output the clock to a general purpose I/O pad, regardless if you're using it for a synchronous interface or not!

The typical way to do what you want is to use a DDR FF, if the device supports it. If it doesn't support it, you might be able to use a 2x internal clock to clock out a toggling 0/1 pattern from the I/O FF.

If none of those are options, the longer answer is that you may not have to specify it the way you are thinking of. What clock rate and how much timing margin do you have? In the past, I have used a MAX_DELAY constraint on the clock net itself, and if memory serves, this actually appeared to make sure the tools routed the clock to the I/O pad with a reasonable amount of prop delay. It won't be 500ps or anything, but it kept the delay in the low single digits.

Have fun,

Marc

Hi, Marc thank you for your answer.

Yes, I have used DDR clock forwarding, but then it gets device dependent. Maybe I have to go for that here too.

OK, I have used MAXSKEW on my clock, but I'll look into maxdelay as well.

Sure I will! :-)

Hakon