powerPC simulation

Hello, am New to PCB board design cycle. Working on circuit having powerPC interfaced with nand flash,FPGA,DDR and ethernet ASIC. I have to do the cycle accurate Functional simulation of the above circuit. How should i go for it? Queries:

  1. Which tool i should use.
  2. Do i need to convert schematics into verilog?
  3. Do i need Models for all the components in the circuit. What is the procedure for doing functional simulation. Also Need to write test code for boot straping,memory mapping(initial registers setting file)and GPIO and the same can be used while emulation further. Experts Kindly guide me. Thanks in advance.


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These are electrical design issues, not CAD ones particularly, although there are CAD enabled tools to help with such simulations, for the simple reason the PCB itself is a major circuit element at higher speeds.

  1. Don't rely on a simulator too much when you are setting length (and match) rules. Calculate them yourself. A decent calculator and a spreadsheet will get you there.
  2. You will have to calculate your timing budgets *before* committing to layout. You can simulate the entire thing and see just what will happen.
  3. Most tools that permit such simulation require that the entire design (at the interconnect level) be modeled; sometimes that's Verilog, sometimes VHDL, sometimes Spice, sometimes a mixture of all three and sometimes a separate description language fromt he vendor.
  4. Yes, you will need models for everything in the circuit. Logic (HDL), IBIS and Spice at least for a full simulation. These give nice information about circuit behaviour even if you aren't running simulations.
  5. As it's a number of years since I bothered using such tools, I can't recommend a particular one. I specify what the circuitry must achieve (see 2), subtract what the parts will do (for FPGAs, I get timing analysis from the tool anyway) and I am left with what the PCB must achieve. I get that by setting layout rules at the schematic level and ensuring they are followed. i.e. Timing meets constraints by initial design.



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Hello, Thanks all for the responses. I do understand the stage for checking timing parameters while calculating the signal delay on the board. But that will come while doing timing simulation / post layout simulation(with IBIS) with the tools like Hyperlinx etc. Please correct me if i am wrong. And we can use emulator for the initial prototype testing. But the current task is checking the functional response of the circuit which has PPC interfaced with Memories,FPGA. What i understood is

  1. Take schematics and convert it to Verilog netlist
  2. Get models for PPC(Swift model) and behaviour models for memories, BFMs for other modules.
  3. Simulati> san wrote:
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