I am designing a frame grabber .The frame input is expeted at a very slow rate of 10mbps. I have 4 state machine strutures running at plb clock rate of 80mhz. I am not able to synchronize the capture of the packets properly. I am using a triemac ip from xilinx. The triemac works fine and does take in all the packets. However I get problem in the state machine part. The out put of state machines doesnt give proper results. When I run xps I get following warnings :
1) wwww may have excessive skew because 73 NON-CLK pins failed to route using a CLK template2) xxxx may have excessive skew because 3 CLK pins failed to route using a CLK template.
3) yyyy may have excessive skew because 10 CLK pins and 6 NON_CLK pins failed to route using a CLK template. wwww is a 2.5mhz clock signal( triemac ) dervied from 25mhz onboard clock by using a simple counter.This is the rate at which input is coming in. The signals xxxx and yyyy are asynchronous signals which are gating the state machines.These signals are running at far lower rate . Should I use bufg or FDDRs to route these signals to statemachines ?-D