I am trying to increase the clock frequency of my microblaze processor (currently 50 MHz) using the dcm_module frequency M/D outputs (CLKFX). I have pasted the dcm_module portion of my system.mhs file here:
BEGIN dcm_module PARAMETER INSTANCE = dcm_module_0 PARAMETER HW_VER = 1.00.a PARAMETER C_CLKFX_MULTIPLY = 12 PARAMETER C_CLKFX_DIVIDE = 10 PARAMETER C_CLKIN_BUF = TRUE PARAMETER C_CLK0_BUF = TRUE PARAMETER C_CLKFX_BUF = TRUE PARAMETER C_EXT_RESET_HIGH = 1 PARAMETER C_CLKIN_PERIOD = 20.00000 PARAMETER C_STARTUP_WAIT = TRUE
PARAMETER C_FAMILY = spartan3 PORT RST = net_gnd PORT CLKIN = sys_clk PORT CLKFB = dcm_module_0_CLKF0 PORT CLK0 = dcm_module_0_CLKF0 PORT LOCKED = system_dcm_LOCKED PORT CLKFX = sys_clk_s END
For some reason, during the place and route phase, I get the following errors:
-------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels
--------------------------------------------------------------------------------
- NET "bufgp_73/IBUFG" PERIOD = 20 ns HIGH | 20.000ns | 69440.000ns | 2
50% | | |
--------------------------------------------------------------------------------
- PERIOD analysis for net "dcm_module_0/dcm | 15.384ns | 46398.083ns | 7 _module_0/CLKFX_BUF" derived from NET "b | | |
ufgp_73/IBUFG" PERIOD = 20 ns HIGH 50% | | |
--------------------------------------------------------------------------------
Why is the IBUFG being delayed for 69440 ns?!?!?! I also saw this warning a little earlier in the PAR:
WARNING:CLK Net:sys_clk_BUFGP may have excessive skew because 1 NON-CLK pins failed to route using a CLK template.
Can anyone give me any insight as to why I cannot increase the clock frequency and I get these errors? When I use this same wiring scheme and use a 1X multiplier (M=10/D=10) I can pass the PAR just fine with a
15 ns delay at that IBUFG. What am I missing?