Xilinx DFS woes

Hi Uwe, Did you connect the clock to an IOB? If you connect it to things that aren't dedicated clk pins you'll see warnings like that. You can use the FPGA editor tool to see where the clock net connects. HTH, Syms.

clk connects to Pin 82 (IO_L11P_2/D2/GCLK2) on a XC3S500E-208. Config mode is Serial Master, so the dual mode function D2 should not be used. As shown, I normally don't instantiate Clock Buffer, but while fiddling around I also tried that with no avail.

For a test I connected the DFS input to some other (non-clock) FPGA input, and clk was routed with a global net.

I use webpack 9.1 on suse 10.2. I already tried to run fpga_editor, as your answer in another thread found with Google groups suggests. Starting fpga_editor however makes the disk spin and the CPU work for a while, a window flash up and disappear immediate. I tried also the DISPLAY =:0 trick, but to no avail.

Thanks

Hi Uwe, So the clk comes out of the FPGA on Pin 82, right? If that's the case, you should probably use the IOB's DDR registers to get the clock out. If you wire the data input of the rising edge DDR FF to '1' and the input to the falling edge FF to '0', then connect the clock to the clk input of both, the clock will appear on the output and your clock net will only connect to clk pins. HTH, Syms.

clk is a input. An oscillator is connected on pin 82.

Hi Uwe, OK, in that case my advice is useless!

So, does your cct look like?

IOB ---> clk ----> bufg -|--> DCM ---> bufg ----> clk8 | |--> FFs, etc.

Cheers, Syms.

As my code example showed, I like to write code without instantiating manufacturer specific code. So I let it to ISE to invoke the BUFGs. Obviously it doesn the right thing when no DCM is connected to the GCLK input pin, and it does the right thing for the output of the DCM. However with the DCM, I need to explicitly instantiate the BUFG between the GCLK input and the DCM to use the output of the BUFG to drive the clock nets.