Software controllable clock generator, Xilinx Virtex-II

(snip)

If you start from a higher frequency, and use the divide by 1.5, 2.5, etc. circuits that Peter Alfke has shown in some Xilinx notes, you should be able to get pretty many frequencies in that range. Do the frequencies need to be integer multiples of 1MHz?

-- glen

I don't know much about the DCMs, but if you can use a 1 MHz ref, you should be able to use a PLL with a divider in the feedback loop to generate any multiple of 1 MHz between 43 and 85 MHz. Then the output can be divided down to many other frequencies including all the multiples of 1 MHz below 43 MHz. Will the DCM accommodate a 1 MHz ref and 43 to 85 MHz output?

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Rick "rickman" Collins

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glen herrmannsfeldt wrote: >

Can you point me to those APP notes? Fast divide by N.5 may help indeed, but I can't find a da[r]ned thing on the Xilinx web site.

I figure that if I used clock dividers to get 85MHz and 84MHz, I would need a phase accumulator accurate to 140pS. i.e.

7.14GHz / 84 == 85MHz, 7.14GHz / 85 == 84MHz, ...

which gets me the precision I want at the high end (and more then I need at the low end) but an absurd FX frequency.

Or if I started with 340MHz (Which is still more then I can get out of a -4 DCM)

340MHz / 4 == 85.0MHz, 340MHz / 5 == 68.0MHz, 340MHz / 6 == 56.7MHz 340MHz / 7 == 48.6MHz 340MHz / 8 == 42.5MHz 340MHz / 9 == 37.8MHz 340MHz /10 == 34.0MHz 340MHz /11 == 30.9MHz, ...

I can get more accuracy then I have now (which I can fill in with another DCM and dividers) but 255MHz is more realistic:

255MHz / 3 == 85.0MHz 255MHz / 4 == 63.8MHz 255MHz / 5 == 51.0MHz 255MHz / 6 == 42.5MHz 255MHz / 7 == 36.4MHz 255MHz / 8 == 31.9MHz 255MHz / 9 == 28.3MHz, ...

which makes a large gap of frequencies in the high end of my desired range. I should be able to fill in these gaps with more DCM devices with different (without common integer multiple!) frequencies divided down. This was my original plan. With 3 DCMs and some frequency dividers, I can get pretty good coverage at the low end, with sparse (but adequate) coverage at the high end.

I guess I was hoping for a mathematical miracle to clean up my tangled web of DCMs, BUFGMUX's and frequency dividers.

Boy, would a software controllable DCM be nice here. Unfortunately, I ain't got a V4, I got what I got, a VirtexII, and the slow speed grade at that.

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(snip regarding generating a variety of different clocks from a small number of DCMs.)

But only 170MHz with the half frequency dividers.

So they don't need to be integers.

Note that the relative frequency difference is smaller at the higher frequencies if you keep the 1MHz increment.

20MHz to 21MHz is a 5% increase, so is 80MHz to 84MHz.

If you only need steps that are at most 5%, and not required to be integers then I think it works with a reasonable number of dividers and DCMs.

-- glen

Peter Alfke did a design were he build a phase accumulator running at a few hundred MHz to generate a square wave with almost arbitrary frequency but a few ns jitter. If you feed the result threw a DCM apparently the jitter is reduced to about 100ps. That should be good enough for your application.

Kolja Sulimma

"Kolja Sulimma" schrieb im Newsbeitrag news:41bb8bc2$0$16030$ snipped-for-privacy@newsread4.arcor-online.net...

Are you sure? I thought that the DCM does NOT reduce jitter and furthermore has very tight input jitter reqirements (300ps cycle to cycle, 1ns periodic max.) Its a DCM, not a PLL.

Regards Falk