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warning place and route ise7.1?

Hey,

I want to make a very low frequency signal from a 100Mhz clk signal (since the rest of the logic has to work on this frequency) and i thought using a SRL16E as on-hot-signal shifter and then by placing them right i could easily divide the 100Mhz clk to very low frequencies and then bring it in a global clk net by using a clk buffer but when i do it i get the following warning (it works so this is just because i want to know what they mean with this warning):

WARNING:Route - CLK Net:clk_pwm_OBUF

may have excessive skew because 1 NON-CLK pins

failed to route using a CLK template.

What do they mean with clk template?

Thanks in advance,

Greetz,

Y
Reply to
Yttrium
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What kind of Xilinx FPGA do you use? Most Xilinx FPGA device, Spartan and Vertex, have DLL(PLL). If you want to divide clk, you should use internal DLL to reduce skew and easy use. If else, you should use IBUFG(clock input buffer) for input and OUBF(output buffer) for output.

Reply to
donghun

i'm not using a DLL/PLL because they can't divide the clk that low ... and i'm already using a clk buffer ...

Reply to
Yttrium

Greetz, don't use the DLL or PLL, their division rate is much too small. You seem to concatenate several SRL16s, each dividing by 16, so that 5 LUTs divide by over a million. That probably means that you ripple the clock, and end up with a very slow (=low-frequency) output that has no clear phase relationship with your original 100 MHz. Depending on your application that may or may not be acceptable. You can also re-synchronize after each SRL16 and thus keep a tighter phase relationship. I worry about the functional stability of a 1-of-16 SRL16. Theoretically it will recirculate a single1 forever. But what if it loses its token, or what if it picks up another stray 1? There seems to be no mechanism that fixes that automatically. I prefer circuits that recover from a disaster. I once looked at a 32-bit divider consisting of two SRL16s as LFSR counters, and a 5-bit counter that detects the unique pattern of 32 zeros. I think it fits into one CLB (4 slices = 8 LUT-FFs)

Peter Alfke, Xilinx Applications

Reply to
Peter Alfke

This means that the global net (output of your BUFG or BUFGMUX) is routed to something other than the clock input of a slice or IOB. If you are using the buffered global signal to directly drive a LUT input (gate), or the D of a flip-flop, or the I of an OBUF you will get this warning which indicates that the route uses some potentially high-skew routing resources.

A common cause for this is when routing a clock off the chip. On Virtex 2 and Spartan 3 you can use DDR output flip-flops to avoid the warning. My guess is that your signal is too slow for the routing to matter unless external signals are sampled on the same edge of the clock as they are produced on.

Reply to
Gabor

you're right i got this SRL16E idea somewhere on the xilinx site (i remember reading something about it some months ago) and this seemed a good reason to give this idea a try since i need such slow signal (for very local logic + outside clk) ...

and indeed there is no fixing mechanism ... i like the idea about the lfsr and the counter ... i'll check it out ... anyway thanks for your response ...

kind regards

Reply to
Yttrium

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