I have a 25mhz clock which I have to convert to 2.5 mhz clock and 1.25 mhz clocks. I used DCM module but I get the following warnings. I use dplain counter method but it generates excessive skew on the signals. Is there a way to remove the warnings in the DCM or to remove the excessive skew. Thanks, D
I get the following warnings when I use DCM module:
WARNING:Timing:3234 - Timing Constraint "TS_dcm_module_0_dcm_module_0_CLKDV_BUF = PERIOD TIMEGRP "dcm_module_0_dcm_module_0_CLKDV_BUF" TS_gmii_rx_clk * 10 HIGH 50%;" fails the maximum period check for input clock dcm_module_0_CLKDV to DCM my_peripheral/gig/dcm1/DCM_INST because the period constraint value (400000 ps) exceeds the maximum internal period limit of 41668 ps. Please reduce the period of the constraint to remove this timing failure. WARNING:Timing:3236 - Timing Constraint "TS_dcm_module_0_dcm_module_0_CLKDV_BUF = PERIOD TIMEGRP "dcm_module_0_dcm_module_0_CLKDV_BUF" TS_gmii_rx_clk * 10 HIGH 50%;" fails the maximum period check for output clock my_peripheral/gig/dcm1/CLKDV_BUF from DCM my_peripheral/gig/dcm1/DCM_INST because the period constraint value (800000 ps) exceeds the maximum internal period limit of
666670 ps. Please reduce the period of the constraint to remove this timing failure.Device Utilizati> I have a 25mhz clock which I have to convert to 2.5 mhz clock and 1.25
snipped-for-privacy@gmail.com schrieb:
Yes. Generate clock enables using counters and run everything at 25 MHz.
Regards Falk
I tried using clock enables but still no luck . It still gives me warning indicating excessive skew on the clocks. I also get following warning : This design either uses more than 8 clock buffers or has clock buffers locked into primary and secondary sites. Since only one clock buffer output signal from a primary / secondary pair may enter any clock region it is necessary to partition the clock logic being driven by these clocks into different clock regions.
Even some signal which are not clocks but just enables which drive state machines get slotted as clock signals. Why is that ? How can I prevent that from happening? Thanks, D
Falk Brunner wrote:
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