ISE7.1 PAR Warinng: excessive skew because 1 NON-CLK pins...

If you use FPGA Editor you can select the clock signal and list what pins are on it. Look for odd pin names on the list is one way. On a clock you do get a lot of pins listed. Organised by delay the non-clock pins may be also at one end of the list. If you look at the logic naming where the clock is used as logic input then you should hopefully get an idea where the problem lies.

One possibility is that it has been used as a gated clock and it will go into a LUT with some other signals. You often find this in IP that was originally written for ASIC. Another possibility is that a clock inversion has not been properly pulled into the slice logic and a LUT has been used.

John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board.

Michael,

I had a warning like this on the clock signal which is originally routed through the clock pin, but not directly to BUFG, i.e. there was some muxes on the way.

I think the explanation is that BUFGP is IBUFG + BUFG, and if there is logic in between, then the placer fails using a template (i.e. BUFGP). May be your design / core has some gated clocks or any other logic associated with clock muxing.

Hope this helps.

Vladislav.

Check the delay report and follow your net... It's a little easier to look through the text rather than using the FPGA Editor, but sometimes they complement each other.

Jason