Hello, I want to perform a DMA via the Xilinx PCI-X core (64bit/133MHz) to the system's DRAM. Therefore I want to act as a busmaster and transfer
4K-byte blocks (maximum bytecount) in initiator-burst-transfers. The problem is that the DMA can be aborted at any time, so I have to calculate the appropriate new byte-address, request the bus again and so on. This can be a rather complicated design, so my question is: is there any way to simplify a DMA like descriped above or are there any interface-modules for the Xilinx PCI-X core which work as DMA-controller for the core. Futhermore I'm looking for a simulation-model for the PCI-X-bus-side. Thank you for help, Matthias- posted
20 years ago