DMA PCI-X core

Mar 04, 2004 2 Replies
M

Hello, I want to perform a DMA via the Xilinx PCI-X core (64bit/133MHz) to the system's DRAM. Therefore I want to act as a busmaster and transfer



4K-byte blocks (maximum bytecount) in initiator-burst-transfers. The problem is that the DMA can be aborted at any time, so I have to calculate the appropriate new byte-address, request the bus again and so on. This can be a rather complicated design, so my question is: is there any way to simplify a DMA like descriped above or are there any interface-modules for the Xilinx PCI-X core which work as DMA-controller for the core. Futhermore I'm looking for a simulation-model for the PCI-X-bus-side. Thank you for help, Matthias
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E

Hi,

There is a reference design called the "half bridge" which you might consider using. I believe, with all the bells and whistles enabled, it is best implemented for 66 MHz designs.

However, if you are interested in just a very small part of the functionality, you can customize it (pare it down) and end up with something that runs faster.

You can also craft something yourself; if you want to go down that road I invite you to contact me privately.

Eric

Matthias Müller wrote:

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B

The initiator DMA is not too bad. Here's how I do it: One register is loaded with the memory address. The other is loaded with the size. Every clock cycle we have a nonzero size count and are not currently in a DMA transfer/request, the DMA transfer requests. The size register is decremented and the address register is incremented as the data comes/goes. If the transfer finishes early, we still have a nonzero size so it just starts up again.

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