PCI X MSI Capability (XILINX Core)

Jan 28, 2005 1 Replies
K

Hi All, I am simulating a design with PCI X support (XILINX PCI X Core) to test MSI function of the PCI x device I am doing the following things at initialisation stage of the pci x device



  1. read capability pointers for MSI ID
  2. initialise PCI high and low addresses (64 bit)
  3. initialise 16 bit message.
  4. enable MSI in the MSI control register specifying no. of messages in bit [6:4] of MSI control register. I am facing following porblems
  5. The INTA line is not getting asserted. as I am enabling MSI.
  6. but no transaction is happening from the device for sending MSI when internally the interrupt is getting asserted. can anybody tell me if anything I am missing or anything is wrong. Thanks in advance Rgds kedar
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E

Hi,

The PCI-X core will not generate the writes for MSI. You will need to watch the extended status from the core to see if MSI is enabled -- and if so, you will need to have your user application generate the write.

Eric

"Kedar P. Apte" wrote:

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