constraint for PCI & PCI-X core


I have a 100 MHz PCI-X core for Xilinx device. As a part of PCI-X standard the core is also compliant with PCI 33 MHz.

Now I have a problem with the ucf clock frequency constraint. Since I want it to work in PCI-X 100 MHz I constraint to clock of

100 MHz; but then the PCI 33 MHz logic fail to meet the timing constraints.

I can identify the PCI 33 MHz critical paths as the path that goes directly from pad (TRDY#) to a combinatorical logic, and the paths of PCI-X as the paths that start at IOB registers.

How can I relax the constraints starting at a pad and ending in a CLB register ?

ThankX , NAHUM

Reply to
Loading thread data ...

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.