Xilinx PCI Core burst problem


I have designed a CardBus Design, which is very similar to pci with full master functionality. The main aim of this card is to transfer a huge amount of data to and from PC RAM to the CardBus card. But in master read mode I very often get a target retry. The fact of an target retry (in this case the pc is the target) is not abnormal but I have scanned the pci bus and I have seen a lot of target retries in series

-> sometimes more then 100 in a row. This is absolute unacceptable due to the poor bus performance -> so my fifo's run out of data. The common pc memory (ram) is locked from driver and is set as non cacheable.

I hope that somebody can help me in this issue. I am not really sure if this is a hardware or a software (driver) problem.

With kind regards Nico Presser

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Use significantly larger FIFOs. You can end up with the bus locked out while cache flush operations are going on or other operations that use the processor memory interconnect that hooks up to the PCI interface. If there's other PCI activity, changing the latency timer value could help out. Some processors or bridges will retry a transaction rather than hold the bus for a first burst of a series. Some processors take a memory-read-multiple as a one cache-line transaction but prefetch the next cache-line while others interpret the request as 2 cache-lines at once. Read up on your processor's PCI interface.

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We learned the hard way that PCI is just not intended to read at high data rates. Some chipset will even split a single 128-bit read (SSE2 move) of the CPU into two PCI accesses. You can't really expect the chipset to be nicer to your expansion board than it is to the CPU.

I would not really on getting any read bursts larger than a cache line to work without tuning chipset specific registers.

Kolja Sulimma

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Kolja Sulimma

Hi all,

Thank you for your fast response. Meanwhile I have tried another notebook with a different CardBus chipset (TI PCI-1520) and I did not believe what I have seen. Everything was working as it should be. With master read command 1 DW was transferred, with master read line command

8 DW's were transferred and with master read multiple command 4kB in a row were transferred with the maximum of 1 retry after initial request!!!

Nico Presser

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Kolja Sulimma schrieb:




Hi Kolja,

do you know if SSE2 moves would be normally translated to 64 bit PCI(X) transfers or not? I am working with PCI-X ipcore where backend is always 64bits so sometimes I would like the PC host software todo atomic 64 bit read writes but I found no way. It should be doable only with 64 bit OS as the Intel 64 bit extensions are not accessible in 32 bit OSes (so I have understood it at least). I have been reading intel specs, but as far as I understand on 32 bit OS there is no almost no way to force a programatic 64 bit access from the CPU - maybe I missed something. I only looked at CPU commands not the SSE2

as of burst - sometimes it works like magic, as example I see an PCI 64
bit master to transfer 4KB blocks to PC main memory as almost continous
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