Virtex2Pro: Xilinx PCI core mapping error

And still: License status-Full (sourse available). Coregen Generate sourse files (which are including to project) in folder xxx\coregen\pci32_66\verilog\src\xpci ? Or I should including still other files?

When I to "assign CFG[254:249] = 6'b001100;" instead of "assign CFG[254:249] = 6'b001000;" mapping error, and when I to "assign CFG[254:249] = 6'b001100;" instead of "assign CFG[254:249] = 6'b000100;" mapping succes.

But I read in

"Specifically, you need to set bit 251 (towards the end of the file) to logic one instead of logic zero." But it is a bit 252!!! Thanks, Vasiliy Zamyatin

Your PCI cfg file has one bit that needs the be enabled to force the "SOFT_CE" rather than the "HARD_CE" generated by the (absent) PCILOGIC block.

or

As for "full license" I thought no source code *was* available for the PCI core. There's a wrapper that instantiates some of the top-level I/O and registers but the core (.ngo) is still needed since the simulation model probably won't synthesize well (I never tried).

I've always found those caveats somewhat amusing. Does Xilinx write one piece of code to generate the PCI core, and then another piece of code for the simulation model? How do they make sure the simulation code matches the synthesis version? Somehow I doubt there are two separate pieces of code ;)

actually i think there are, the simulation code is generated from edif with special non synthesis primitives.

Antti

Hello,

It is bit 251 (not bit 252) that controls this feature. It is called the "SOFT_CE" bit. If you set it to one, the output clock enable is generated by a 5-input function implemented with two LUT4 and a MUXF5. If you set it to zero, the output clock enable is generated by a component called PCILOGIC which is only present in certain families. As you realize from the error message, V2Pro does not have this PCILOGIC component, so trying to use it results in a DRC error.

There is a section in the Getting Started Guide that discusses this option and how it should be set, based on the target architecture. There are also other important considerations regarding the input delay buffers which merit a close read. I encourage you to review the Getting Started Guide to ensure you have all the information you need to successfully complete a design using this IP core.

Good luck, Eric

Hello,

The netlist and the simulation model are derived from the same source; it would be fair to say the simulation model is cycle-accurate but is not something you will want to try to synthesize -- it has a slightly different construction and won't have any of the attributes that are present in the netlist. These attributes (which you cannot see) are an important part of this highly-tuned IP core to ensure consistency in the results.

Incidentally, if you look at a sample of net and instance names in the timing report when you use this core, you may immediately recognize the source format of the IP core... It's no secret.

Eric

I/O

for