EDK 7.1 : ML40x / ML401 Reference Design

Apr 27, 2005 1 Replies

Rate this thread:

Peter Soerensen 21 years ago

Hi all,

I have just upgraded from the 6.3 version of the EDK to the 7.1 version. For testing purposes i wanted to download the ML40x reference design onto my ML 401 board. Unfortunately, the new EDK (the par tool) seems unable to meet the timing constraints of the design. I dont know if this is a problem with the EDK or ISE

7.1. If anyone out there has found a work around or perhaps a solution I would love to hear about it. I have made no changes to the design.

Thanks peter

Vote

Rudolf Usselmann 21 years ago

I had similar problems initially. With ISE/EDK 6.3, I would increase the effort level for PAR to meet timing.

With ISE/EDK 7.1, I found that adding the "-timing" option to MAP, andusing the default effort for PAR gives me about the same results as with 6.3sp2.

I am just tracing a gcc incompatibility between 7.1 and 6.3 EDK (again). Anybody run in to that yet ?

Best Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services,

formatting link

Your Partner for IP Cores, Design, Verification and Synthesis

Vote

Join the Discussion

Have something to add? Share your thoughts — no account required.

Didn't find your answer?

Ask the community — no account required