Is anybody able to tell me anything about working out the cycle-to-cycle jitter of a DCM output?
The situation is that I want to forward a clock to a QDRII device, which has a cycle-to-cycle jitter tolerance of +-100 ps. The data I can find on the Virtex-II Pro DCMs only specs the period jitter (Which is the upper bound for the cycle-cycle jitter). In addition to that, the user guide states that DCMs cannot remove jitter.
The period jitter introduced by the DCM is too high (CLK0 has +-100 ps period jitter), but the actual cycle-cycle jitter should be lower.
Question is - can it be done? (XAPP750 doesn't seem to consider it as a problem), and the other question is how to spec the jitter characteristics for the clock source.
I'd rather make the design correct-by-design, rather than trying it and characterising it (I don't have hardware yet anyway) - I'd appreciate any light anyone could throw on the matter.