1. Home
  2. Field-Programmable Gate Arrays
  3. DCM Cycle-to-Cycle Jitter

DCM Cycle-to-Cycle Jitter

Is anybody able to tell me anything about working out the cycle-to-cycle jitter of a DCM output?

The situation is that I want to forward a clock to a QDRII device, which has a cycle-to-cycle jitter tolerance of +-100 ps. The data I can find on the Virtex-II Pro DCMs only specs the period jitter (Which is the upper bound for the cycle-cycle jitter). In addition to that, the user guide states that DCMs cannot remove jitter.

The period jitter introduced by the DCM is too high (CLK0 has +-100 ps period jitter), but the actual cycle-cycle jitter should be lower.

Question is - can it be done? (XAPP750 doesn't seem to consider it as a problem), and the other question is how to spec the jitter characteristics for the clock source.

I'd rather make the design correct-by-design, rather than trying it and characterising it (I don't have hardware yet anyway) - I'd appreciate any light anyone could throw on the matter.

Thanks, Jeremy

Reply to
Jeremy Stringer
Loading thread data ...

Jeremy,

The reason why we don't specify the cycle to cycle jitter any longer is that it is hardly used by anyone anymore.

Obviously, you have a a requirement.

I may question how useful it is, but I won't (how does it know, or care what the previous cycle timing was?).

The worst case cycle to cycle jitter (immediate cycle to the next one) is the tap value.

That is ~50ps for V2, and 35 for V2 Pro, and ~25ps for V4.

Add linearly to that value the cycle to cycle jitter on the input clock itself.

So it the input is 20 ps, and the tap is 50 ps, then the total is 70 ps.

Austin

Jeremy Str> Is anybody able to tell me anything about working out the cycle-to-cycle

Reply to
austin

I'd be interested to know what you would consider to be useful in this case - the question that I really needed to answer, of course, is "will these two devices work together". The target DLL in question had a cycle-to-cycle jitter requirement (+-100 ps) that was smaller than the period jitter out of the DCM (particularly when input clock jitter was included).

Thank you Austin :) I appreciate the help - I've been trying to track down parameters for this interface for about two weeks now.

Jeremy

Reply to
Jeremy Stringer

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.