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Spartan-3E, ISE 7.1 some issues - solved (BUFG insertion problem)

Hi

I think some others have seen this problem with ISE 7.1 as well, the 'auto BUFG' insertion logic is changed from 6.3 to 7.1 this makes some designs that used to work with 6.3 to not pass route in 7.1 (Global clock overmapping) if that happens there is a very simple way to avoid this the false nets where the BUFG should not be used must be flagged with "buffer_type" attribute set to "none"

that fixes the problem

Antti PS I found the problem while testing 7.1 for S3E readiness, but then the problem also appeared with the same design on S3, so its the overall issue of the 6.3 vs 7.1 - I guess its not even a bug but feature, and not a problem when you know it.

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Antti Lukats
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ISE Service Pack - Service Pack #3 is the latest Service Pack fo Xilinx ISE 7.1i. Download the available file to ensure that you Xilinx software is up to date

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elcielo

"elcielo" schrieb im Newsbeitrag news:QeSdnWH_a6kpGlLfRVn snipped-for-privacy@giganews.com...

the issue was actually observable also with 7.1SP2 and spartan3, and Xilinx response was that the issue is most likely not addressed in SP3 as it was rather rare case:

  • 32 bit counters (n number of them) all clocked from different clocks, use n global clocks
  • JTAG BSCAN, some outputs auto promoted to use BUFG by 7.1 SP2

as ISE inserted BUFG on DRCK1 from BSCAN then total number of global clocks exceeded 8, and as the 32 bit counters as RPM do not fit into a quadrant then the resulting design did not route. (limitation of global clocks that can enter a single quadrant)

to my surprise the issus has been solved in SP3, the designs do not fail any more on routing, but without manually setting 'buffer_type' the auto allocation of the BUFG is wrong, so I still need to manually 'disable' some of the BUFG insertion.

in SP3 8 clocks are selected to be Global (at random?) the rest goes with local routing, when 'false' clocks as are set to buffer_type=none then the actual clocks are detected ok

Antti

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Antti Lukats

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