I'm using EDK 6.3 + SP2, along with ISE 6.3 + SP3 + IP updates 4 + XFFT patch.
Yes, I had no problem building the reference design, and no problems adding my own plb peripherals. I'm working on a sonar beamformer app. using plb peripherals with xfft3_1. My problem was that the reference design included many cores that I didn't need, and my plb peripherals were getting pretty big (big FFTs), so I wanted to strip down the reference design. However the resets and clocks for different parts of the reference design were all a bit coupled (misc_logic, sys_proc_reset etc.) so I initially had difficulty separating things out. Because I couldn't find an XBD file, last week I started from scratch with a new XPS project, adding only the ip I needed, and making my own entities with DCMs for the system, plb and ddr sdram clocks. I used the reference design's constraints file (system.ucf) as a guide - its working fine.
I think the reference design uses some deprecated cores - only thing I can think of is perhaps you accidentally changed these to newer versions which aren't compatible? - In Xilinx Platform Studio, did you go into 'add/edit cores' and accidentally upgrade these cores?