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EDK 6.3, Xilinx ML40x ML402, XBD files

Hi All

Does anybody know if an XBD file is available for the Xilinx ML402 board? I'm currently using EDK6.3 - I'd also be grateful if someone could tell me whether a BSP for this board comes with EDK7.1.

I've been adding my own plb peripherals to the Xilinx ML402 reference design, but I've reached a stage now where I really need to start afresh with a smaller design. Synthesis and implementation are taking too long, and aside from my own peripherals, I only really need an opb2plb_bridge, plb_ddr and perhaps a uart for debugging.

Best regards

Allan Willcox

Reply to
Allan Willcox
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HI Allan,

I am myself looking for the same. Am using EDK6.3/ISE6.3i. I am also told that there is no XBD included even in EDK7.1 for the ML402 board.

Allan, were you able to build the reference design without any errors? For me, the reference design generates lots of errors about unavailable versions of peripherals referenced in the design. What service packs are you using.

Any help appreciated.

TIA,

Abhishek

Reply to
abgoyal

I don't know who told you that the XBD for ML402 isn't included in EDK7.1, it is included in my EDK7.1 (sp 1). I was also able to build it and run it on my board without changing anything or experience any sort of error. I guess this is not very helpful indeed, but at least I can say that it works using sp1...

cheers! Johan

--
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Johan Bernspång, xjohbex@xfoix.se
Research engineer

Swedish Defence Research Agency - FOI
Division of Command & Control Systems
Department of Electronic Warfare Systems

www.foi.se

Please remove the x's in the email address if
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Reply to
Johan Bernspång

I'm using EDK 6.3 + SP2, along with ISE 6.3 + SP3 + IP updates 4 + XFFT patch.

Yes, I had no problem building the reference design, and no problems adding my own plb peripherals. I'm working on a sonar beamformer app. using plb peripherals with xfft3_1. My problem was that the reference design included many cores that I didn't need, and my plb peripherals were getting pretty big (big FFTs), so I wanted to strip down the reference design. However the resets and clocks for different parts of the reference design were all a bit coupled (misc_logic, sys_proc_reset etc.) so I initially had difficulty separating things out. Because I couldn't find an XBD file, last week I started from scratch with a new XPS project, adding only the ip I needed, and making my own entities with DCMs for the system, plb and ddr sdram clocks. I used the reference design's constraints file (system.ucf) as a guide - its working fine.

I think the reference design uses some deprecated cores - only thing I can think of is perhaps you accidentally changed these to newer versions which aren't compatible? - In Xilinx Platform Studio, did you go into 'add/edit cores' and accidentally upgrade these cores?

Best regards

Allan Willcox

Reply to
Allan Willcox

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