DCM multiplier and EDK design

I have a Xilinx EDK based design for a Virtex II Pro using the PowerPC Processor. There are two DCMs in the processor subsystem, as defined by the mhs file. The first one, takes a 10MHz clock from the board and multiplies it by 8 to create an 80 MHz clock that runs all of Processor/PLB/OPB stuff. The second DCM just creates a deskewed,

90-degree-shifted version of that clock, for the DDR SDRAM.

I am trying to boost the speed to 100 MHz by changing the multiply factor to 10. I have encountered 2 problems.

1. The 100 MHz clock won't run reliably unless the board is power cycled before loading the FPGA image. I also tried a factor of 20 (200 MHz) and it does the same thing. Any of the three speed clocks (80 MHz,

100MHz, or 200 MHz) will run properly if the board is power cycled and then the FPGA is loaded with the image. However, if the image is reloaded with power on, only the 80 MHz clock will run at the correct speed regardless of what image was loaded first. If the 100 or 200 MHz image is loaded after a different speed clock image, the resulting clock is either wrong or not running at all. In all cases, I bring the clock out to a test pin to verify the speed with a scope. I assume this points to some sort of reset issue with the DCM?

1. If I power cycle to ensure a 100 MHz clock, I can't run any program - the debugger loses contact with the system mmediatlely. At this point, the 80 MHz and 100 MHz designs are exactly the same, except for the multiply factor on the DCM and the obvious clock speed related parameters on the varioius cores (plb-ddr and emc mainly). My program is entirely in BRAM so only that and the UARTlite need to run to at least see 'life' from the program.

My reading of the specs and Xilinx docs so far, doesn't indicate there is anything else that would need to change for this to run. I am currently reading those again to see if I've missed anything. The original design was started with the Base System Builder, which didn't allow a processor clock higher than 80 MHz from a 10 MHz input. I guess that might be a clue, but the spec sheets don't indicate such a limitation. I am more of a software guy at this point and new to FPGAs, so any general guidance on proceeding to debug this is appreciated.

Any clues or sugggestions?