DCM and domain crossing

Hi,

I have a question regarding Xilinx DCM. If a clock signal is generated by DCM (say 2X) and used to drive another clock domain. Is the new domain still ?synchronized? with the original clock domains? Do I need to insert synchronization circuit when a signal crossing form 1X domain to 2X domain and vice versa?

Thank you in advance.

Will G.

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Anonymous via the Cypherpunks Tonga Remailer
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Reply to
viswanathank

This depends on your clock routing and buffering. The 1x and

2x clock outputs (0 phase) at the DCM have coincident rising edges. Thus if your two clock domains use the dedicated global routing resources from both outputs of the same DCM (this may require hand selection for BUFGMUX components to minimize skew), you don't need to re-synch when crossing from one (rising-edge) domain to the other. You should be careful with timing constraints because a PERIOD constraint on the 1x domain would usually indicate that the signal does not need to be stable at the falling edge of the 1x clock where the 2x clock has another opportunity to sample. I usually use a clock enable on the 2x clock domain to ensure that it only samples the 1x signals where the rising edges are coincident.

HTH, Gabor

Reply to
Gabor

In a perfect world, yes, they are aligned. However, if you have clock jitter on the clock going into the DCM, it is possible for the edges to lose alignment, at least on the older CLK_DLLs. I got bitten badly on that when Xilinx first introduced the Virtex line...they assured me that the clocks were aligned, but as it turned out, clock jitter at the DLL input can cause misalignment beyond the alignment spec. In my case we were seeing a large misalignment of several hundred ps, enough to make the design fail. It turned out that jitter was getting introduced onto the clock by a bunch of outputs switching on the same bank as the single-ended clock input, and that jitter was in turn causing the 1x and

2x outputs to go out of alignment.

The moral of the story is, be careful and conservative in your design.

Reply to
Ray Andraka

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