I have a 25 mhz onboard clock. I need a 2.5mhz clock to be generated from it. I tried using DCM with CLk_DV value of 10. but it gives me the following error. Type of C_CLKDV_DIVIDE is incompatible with type of 10.
I used a counter inside the fpga to generate the clock but it gives me too much skew problems.
I tried searching for application notes to add DCM into the design but couldn find one or Virtex II pro.