board : Avnet Xilinx Virtex-II Development Kit fpga : Xilinx Virtex II Pro 20 ==> 2 ppc405, and so on ...
problem : avnet includes a ucf file for this FPGA stating the physical pinning for an externally attached ddr sdram of 128MB With Base System Builder Wizzard in EDK/XPS I create a design for the virtex II Pro 7, they haven't got one for the 20 ... Since the 7 and the 20 FPGAs have the same package I suppose their pinning should also be the same, this I can conclude out of the UCF files Avnet gives with the board for either 7 or 20 ... After my design wizzard has finished and I have attached a ddr 64x16 controller for the DDR the UCF file doesn't match the one provided by avnet ... So far not so good ... I use the controller anyway, and bring out my signals out of the processor design towards the top level VHDL design created in ISE ... I bring out those pins with buffers attached to them out of the toplevel design and try both constraints ... the one BSB has created and the one discribed in the UCF given with the board. When I address the controller, it returns 0xffffffff .. meaning there is no connection with the DDR SDRAM
Uptill now I have used the shared bus SDRAM, but since i need my PCI connection and I cannot transmit data into the Virtex without using the SRAM connected to the pci bridge, and since both 2MB SRAM and 32MB SDRAM are on a shared bus, this will affect speed, because I need a big memory to buffer in and output ... therefor I want to connect the 128MB DDR SDRAM to the PLB bus connected to the PPC controlling transfer In and Out the card.
My question : how can I connect the DDR mem ... Did I do something worng, has someone encountered the same problem with this board
thx in advance,