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Daft modelsim question

I'm trying to simulate some Verilog to run on my XPort card. The card plugs into a Gameboy, so any configuration of its FPGA has to include a couple of provided blocks for interfacing to the Gameboy's bus.

So the program begins `include "primary.v"

When I try compiling this in modelsim, it says it can't find primary.v, even if I figure out where in my directory heirarchy primary.v is hiding and add it to the modelsim project.

So, how do I set what in C I'd call the include directory? The manual suggests I should use the compile -> compile options... menu option, but that's greyed out.

Sorry to ask such a dumb question,

Tom

Reply to
Thomas Womack
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Try this when you compile:

vlog +incdir+ file.v

Pete

Reply to
Pete Sedcole

Try adding the file to the Modelsim project by compiling it first into your work library.

Reply to
yyy

Why are you including a verilog source in a verilog source? That's like including a C source in another C source.

Simply add primary.v to your modelsim project.

-a

Reply to
Andy Peters

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