I would like to access environment variables defined in ModelSim (6.0d) in my Verilog code so that I can use them with the `ifdef construct. For instance, ModelSim allows you to access the "MODEL_TECH" environment variable, which is useful for employing `ifdef's on code you want that you want to be compiled for simulation, but ignored for hardware synthesis.
In a similar vein, I tried creating and setting my own environment variable using "setenv MY_VARIABLE 1" in my .do compile tcl script right before the script compiles my modules. Unfortunately, the Verilog code is not able to access this env variable. I'm avoiding using an include file, but if there is not way around this, then that's what I'll have to do.