Memory Initialization Files in Modelsim

Consider using the standard vhdl templates to infer block rom or ram to eliminate the MegaWizard simulation hassles.

-- Mike Treseler

If you have used the Megawizard PlugIn Manager and specified that the memory should be initialized along with the correct hex file, there is no additional step needed, to specify the memory files to Modelsim. You can verify this by opening the VHDL or Verilog file written out the Megawizard and check the INIT_FILE parameter. Its value should be the path to the hex file.

If you are using Modelsim SE/PE then use the following vcom commands in Modelsim (This is taken from the Quartus online help)

For VHDL 87-compliant designs:

vcom -work work \220pack.vhd vcom [-87] -explicit -work work \220model_87.vhd vcom -work work \altera_mf_components.vhd vcom [-87] -work work \altera_mf_87.vhd vcom -work work .vhd vcom -work work .vhd

For VHDL 93-compliant designs:

vcom -93 -work work \220pack.vhd vcom -explicit -work work \220model.vhd vcom -work work \altera_mf_components.vhd vcom -93 -work work \altera_mf.vhd vcom -work work .vhd vcom -work work .vhd

where path to library would look like d:\quartus30\eda_simlib.

Hope this helps.

- Subroto Datta Altera Corp.

Hello,

thank you for your answer. I've tried out the following MACRO:

cd H:/EDA/Altera/USB/Packetfile_Ctrl/simulation/modelsim vlib modelsim_work vmap work modelsim_work vsim TB_CHECK_TRANSFER vcom -93 -work work {D:/Programme/QuartusII/eda/sim_lib/220pack.vhd} vcom -explicit -work work {D:/Programme/QuartusII/eda/sim_lib/220model.vhd} vcom -work work {D:/Programme/QuartusII/libraries/vhdl93/altera_mf_components.vhd} vcom -93 -work work {D:/Programme/QuartusII/eda/sim_lib/altera_mf.vhd} vcom -work work {H:/EDA/Altera/USB/Check_Transfer/CHECK_TRANSFER.vhd} vcom -work work {H:/EDA/Altera/USB/Check_Transfer/simulation/modelsim/TB_CHECK_TRANSFER.vhd} view signals view wave vsim work.TB_CHECK_TRANSFER run 15000ns

I get the following error message when executing the MACRO:

# -- Compiling architecture lpm_syn of lpm_ram_dq # ** Error: D:/Programme/QuartusII/eda/sim_lib/220model.vhd(3586): FILE declaration using 1076-1993 syntax. Recompile using -93 switch. # ** Error: D:/Programme/QuartusII/eda/sim_lib/220model.vhd(3586): VHDL Compiler exiting # ERROR: D:/Programme/win32aloem/vcom failed. # Error in macro H:\EDA\Altera\USB_Extender\Check_Transfer\simulation\modelsim\tb_run.do line 6 # D:/Programme/win32aloem/vcom failed. # while executing # "vcom -work work {D:/Programme/QuartusII/eda/sim_lib/220model.vhd} # "

Regards Andres Vazquez G & D System Development

Hi again,

sorry I have made an mistake in my MACRO: Now I can execute the MACRO correctly, but nevertheless the output of the RAM structure is 'X' in the simulation, that is no initialization has be made on the RAM.

Kind regards Andres Vazquez G & D System Development

cd H:/EDA/Altera/USB/Packetfile_Ctrl/simulation/modelsim vlib modelsim_work vmap work modelsim_work vsim TB_CHECK_TRANSFER vcom -93 -work work {D:/Programme/QuartusII/eda/sim_lib/220pack.vhd} vcom -explicit -work work {D:/Programme/QuartusII/eda/sim_lib/220model.vhd} vcom -work work {D:/Programme/QuartusII/libraries/vhdl93/altera_mf/altera_mf_components.vhd} vcom -93 -work work {D:/Programme/QuartusII/eda/sim_lib/altera_mf.vhd} vcom -work work {H:/EDA/Altera/USB/Check_Transfer/CHECK_TRANSFER.vhd} vcom -work work {H:/EDA/Altera/USB/Check_Transfer/simulation/modelsim/TB_CHECK_TRANSFER.vhd} view signals view wave vsim work.TB_CHECK_TRANSFER run 15000ns

{D:/Programme/QuartusII/libraries/vhdl93/altera_mf/altera_mf_components.vhd}

{H:/EDA/Altera/USB/Check_Transfer/simulation/modelsim/TB_CHECK_TRANSFER.vhd}

It is difficult to pinpoint the cause without seeing the design and the vectors. For a start make sure that the input signals(waveforms) being fed into the memory have the correct timing requirements, and if there is an enable signal it has been set to the right value. Also if the memory is being simulated as part of a larger circuit, simulate the memory as a separate project and verify that ir works before simulating the whole circuit. Hope this helps.

- Subroto Datta Altera Corp.

Dear Mr Datta,

thank you for your answer. I have looked at the memory ini file during compilation and I get the following warning message: "Warning: Memory depth value (1024) in design file differs from memory depth value (32768) in Memory Initialization File - truncated remaining initial content value to fit RAM"

The used RAM has the following input / output widths: input wrdata[0..0] (quasi one single bit) input wraddress[14..0]

input rdaddress[9..0] output rddata_q[31..0]

So I used a .mif file of 32768 words á 1bit = 32768bits (initialized with zeros). Why is the depth of the RAM said to be 1024?

Thank you in advance.

Best regards

Andrés Vázquez Guntermann & Drunck System Development