Altera DDR Controller, Modelsim and Verilog

Hi Forumees,

Anyone have any experience simulating the verilog model of the DDR SDRAM Controller in modelsim?

I am trying to use the following command -

#compile the encrypted ddr controller in the work #dir vlog ${ddrc2_ctl_dir}/_src/ddr_c2_sctl.vo

#re-compile ddr controller in work directory #this substituting the white-box blocks in #the database vlog ${ddrc2_ctl_dir}/_src/ddr_c2_sctl_example_top.v \

+libext+.v+.vo -y ${ddrc2_ctl_dir}/_sim \

-y ${ddrc2_ctl_dir}/_sim/testbench \

-y ${ddrc2_ctl_dir}/_src \

-y ${ddr_sdram_megacore_rootdir}/lib \

-v $env(QUARTUS_ROOTDIR)/eda/sim_lib/altera_mf.v \

-v $env(QUARTUS_ROOTDIR)/eda/sim_lib/220model.v \

-v $env(QUARTUS_ROOTDIR)/eda/sim_lib/sgate.v \

-v $env(QUARTUS_ROOTDIR)/eda/sim_lib/${sim_family_name}_atoms.v

The command does not have any problems running. But it does not compile the auk_ddr_ctlr module. I do not know why? BTW, I have verified that the tcl variables are pointing to the correct path.

I appreciate any help. Thank you. Best regards, Sanjay

Reply to
fpgabuilder
Loading thread data ...

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.