Hello, I have a question about instantiating a module in a verilog testbench. Sometimes the instantiation may have lots of inputs and output that you may not want to appear in the ModelSim simulation, is there a way to stimulate particular signals in a module so the simulation won't include (display) all of the i/o in your design. Below if my testbench:
// // Copyright 2006 Mentor Graphics Corporation // // All Rights Reserved. // // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF // MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. // `timescale 1ns/1ns
module test_counter;
reg clock_80mhz, fiber_rst;
reg delay_clock;
wire pin_in;
ModelSimTopblock dut ( fib_rx_dv, fib_rx_er, fib_rx_clk, reset_fpga, clock_80mhz, fiber_rcv_rdreq, fiber_go_xmit, fiber_wrreq, fiber_rst, pin_in, fib_rx_data, fiber_tx_data, //------------------------------ fib_tx_en, fib_tx_er, fifo_ef_dsp, dsp_fib_rx_interrupt, fib_rx_data_led, fib_tlk_sig_loss, fib_tx_data_led, fifo_ef_ctl, pin_out, fib_tx_data, fiber_data_rcvd );
parameter tON = 15, tOFF = 7;
initial // Clock generator begin clock_80mhz = 0; forever #15 clock_80mhz = !clock_80mhz; end
always begin #tON delay_clock = 0; #tOFF delay_clock = 1; end
initial // Test stimulus begin fiber_rst = 1; #5 fiber_rst = 1; #4 fiber_rst = 0; end
assign pin_in = delay_clock;
initial $monitor($stime,, fiber_rst,, clock_80mhz,,, pin_out);
endmodule
When I launch modelsim all of the io signals of the ModelSimTopblock would be present in the sim. Can I do something like this:
ModelSimTopblock dut ( 0, fib_rx_er, 0, 0 clock_80mhz, 0, 0 fiber_wrreq, fiber_rst, pin_in, fib_rx_data, fiber_tx_data, //------------------------------ 0, 0, 0 0, 0, 0, fib_tx_data_led, fifo_ef_ctl, pin_out, fib_tx_data, fiber_data_rcvd ); Here only a few signals would be stimulated and few signals would appear in the ModelSim simulation window. Is there a way to do this?
thanks, joe